RISC-V Tech Blog

Silicon reviews, MCU tutorials, OpenWrt guides and ecosystem analysis — written for engineers evaluating RISC-V for production.

70 articles · updated September 21, 2026

RISC-V AI2026-09-21·10 min read

Ruixin Gaoguang D35: A RISC-V Dataflow Physical-AI Chip with 128 GB VRAM and >90% Compute Utilization

Suzhou Ruixin's Gaoguang D35 entered mass production in June 2026: fully self-developed RISC-V CPU core + dedicated LPU dataflow processing unit, 128 GB on-chip VRAM, Chiplet advanced packaging, claimed >90% compute utilization. ISCA 2026 best-paper nomination. Qiyuan Robot partnership. Five scenarios: smart security, industrial inspection, embodied robots, autonomous driving, smart storage...
RISC-V AI2026-09-20·12 min read

Inside the SpacemiT K3 Preview Paper: Homogeneous Fusion, X100 + A100, and What 60 TOPS Actually Means

The official K3 preprint (2026-01-29), annotated: X100 (OpenC910 lineage, TAGE, 17-cycle L2 hit, 7 VMs/core) + A100 (VLEN 1024, IME 1.0/2.0 matrix tiers, shared Tensor Core), one SMP Linux with AI-partitioned cores, ONNX Runtime + tile-level Triton, and every benchmark table — SPEC CINT2006 22.88, −5.48% under KVM, GHASH 46.6×, 3.28× memory bandwidth...
RISC-V Datacenter2026-09-19·11 min read

First Mass-Produced RISC-V AI Supernode Goes Live: EVAS Epoch in an Operator Data Center

EVAS Intelligence's 64-node supernode — Epoch chips on E200-L liquid-cooled OAM modules in an orthogonal backplane-free ELink fabric — is now serving MoE traffic in a Shijiazhuang operator data center, backed by a new ~RMB 2B round at a ~RMB 15B valuation. Deployment tables, MoE expert-routing mechanics, the gen-2 roadmap, and a strict vendor-claims vs verified-facts separation...
Dev Tools2026-09-18·10 min read

Andes AX66 Pre-Silicon: Linux KVM + Dual LLM Inference on FPGA Before Tape-Out

Quad-core AndesCore AX66 (13-stage OoO, RVA23, RVH + AIA, CHI) on a single AMD Versal VP1902 in S2C's Prodigy S8-100: 60 MHz, ~55% logic, Linux KVM with two VMs, two TinyStories-42M LLMs running pre-silicon...
RISC-V AI2026-09-17·11 min read

MNN LLM Inference on SpacemiT K3 — IME2 W4B64 Quantization and Benchmarks

Alibaba MNN on SpacemiT K3: IME2 matrix extension, asymmetric W4B64 quantization, TCM double-buffer pipelining; Qwen3-0.6B hits 381 tok/s prefill, 54.49 tok/s decode...
RISC-V Datacenter2026-09-16

SiFive + AMD ROCm on BigSky — RISC-V Head Node Gets Its Second GPU Stack

AMD ROCm 10.0 demoed on the BigSky SF-2U870 (32× P870-D head node + Radeon AI PRO R9700) running Gemma4-E2B at AI Infra Summit 2026. Full hardware spec tables, the ROCm demo stack, and how the AMD path compares with NVIDIA's CUDA port — plus what a RISC-V head node means for AI infrastructure economics.
RISC-V2026-09-15

Infineon Maps RISC-V for Automotive Zone Controllers at Hot Chips 2026 — MCU Island + MPU Island, AUTO-SIG Profiles, and the Three-Architecture AURIX Portfolio

Infineon's Hot Chips 2026 automotive RISC-V architecture talk: zonal E/E architecture transition, MCU island + MPU island heterogeneous zone controllers, RVI AUTO-SIG profiles (RV32E+I+M+U baseline), RVM virtualization for mixed criticality, and the three-architecture AURIX portfolio (TriCore + Arm + RISC-V).
RISC-V MCU2026-09-14·4 min read

Aheesa VIHAAN-I: A RISC-V Broadband SoC Moves From First-Pass Silicon to Packaging Partner

Aheesa's RISC-V broadband SoC VIHAAN-I goes from first-pass silicon to an Optilink packaging MoU, targeting commercial deployment in early 2027.
RISC-V Development2026-09-14·4 min read

Axelera Voyager 1.8 Swaps GNU newlib for LLVM 20 on RISC-V: 10x Smaller Wheels, ~10% Faster Small-Model Inference

Voyager 1.8 replaces GNU newlib with LLVM 20 on Axelera's RISC-V toolchain: wheel drops ~200 MiB to ~20 MiB, up to ~10% faster small-model inference.
RISC-V2026-09-14

EU Cyber Resilience Act Article 14 — 24-Hour Vulnerability Reporting Hits RISC-V IoT

EU CRA Article 14 reporting obligations live Sept 11 2026. 24-hour vulnerability reporting clock, ENISA Single Reporting Platform, €15M / 2.5% global turnover penalty tier, SBOM and CE marking by Dec 11 2027. Scope across all RISC-V MCU, SoC and IoT products shipping into the EU.
RISC-V Development2026-09-14·4 min read

Fedora 45 RISC-V Rebuild: GCC Internal Compiler Errors on SpacemiT K1 and K3 Boards

Fedora's RISC-V group reports GCC ICEs on SpacemiT K1/K3 boards linked to new glibc vector optimisations, while the F45 rebuild stays on track.
RISC-V AI2026-09-14·4 min read

XuanTie Edge AI Solution: Titan 512–4096-bit Vector Engine and a Programmable RISC-V Scheduling Core

DAMO XuanTie's edge AI solution pairs a RISC-V scheduling core with a 512/1024/4096-bit Titan vector engine, 66 vector instructions and 177 operators.
RISC-V2026-09-12

Nuclei Tech (芯来科技) Files for IPO — Global First ASIL-D RISC-V Automotive CPU IP

Nuclei Technology files for BSE IPO. Global first RISC-V CPU IP certified to ISO 26262 ASIL-D. NA900 automotive IP, UX1030H RVA23 high-performance core, 300+ customers, 87% gross margin, 4.85B cash.
Software Ecosystem2026-09-12·10 min read

Rust on RISC-V 2026: Tier 2 with Host Tools + the New riscv64a23 Target

A snapshot of Rust's RISC-V platform support as of September 2026: which targets are stable, which is new, and why the Tier 1 RFC is still open. Practical build instructions and toolchain notes for production Rust on RISC-V hardware.
Datacenter2026-09-11·11 min read

RISC-V Server Chips Enter Production Datacenter: LX500, K3 & JH-B100

RISC-V server silicon moves from lab to production racks. Deep dive into BlueChip LX500, SpacemiT K3, and StarFive JH-B100 — the three chips that target the data center.
RISC-V Development2026-09-09·6 min read

YuzukiNeko Brings Allwinner F101 and a T-Head C907 Core to a Raspberry Pi Pico–Sized Linux SBC

Allwinner's F101 SoC — one 1.008 GHz T-Head C907 RISC-V core, 8–16MB SiP PSRAM — runs mainline Linux 7.2 and Zephyr on a 51×21 mm Pico-sized board.
RISC-V AI2026-09-09·5 min read

CONVOLVE's Chimera Chip: RISC-V Host Plus Memory-Centric and Neuromorphic Accelerators

TU/e's EU-funded CONVOLVE project taped out Chimera: RISC-V cores plus memory-centric and neuromorphic accelerators, validated on fabricated silicon.
RISC-V MCU2026-09-09·5 min read

Espressif ESP32-P4X-EYE Puts a 400 MHz Dual-Core RISC-V Vision Kit in a Camera Shell

Mouser stocks Espressif's ESP32-P4X-EYE: a camera-shaped kit on the dual-core 400 MHz RISC-V ESP32-P4 with up to 32MB PSRAM and H.264.
RISC-V AI2026-09-09·5 min read

NanoCore 3D-CIM: RISC-V Heterogeneous Compute-in-Memory Chips Near Mass Commercialization

Hangzhou NanoCore closed a ¥1B C1 round for 3D-CIM AI inference silicon combining DRAM near-memory, SRAM CIM and RISC-V. TOPS and node undisclosed.
RISC-V MCU2026-09-09·5 min read

Nuvoton NPCR1 OpenTitan RISC-V Secure MCU Lands in Antmicro's Renode Simulation Framework

Nuvoton's NPCR1 OpenTitan RISC-V secure MCU is simulatable in Antmicro's Renode, targeting FIPS 140-3 Level 1 and Common Criteria PP0084.
RISC-V MCU2026-09-09·5 min read

Waveshare ESP32-C5 Pico: Dual-Band Wi-Fi 6 RISC-V Board in Pico Form Factor From $8.99

Waveshare's ESP32-C5 Pico puts Espressif's 240 MHz RISC-V Wi-Fi 6 + 802.15.4 SoC on a Pico board. Specs, variants, pricing and toolchain.
RISC-V Datacenter2026-09-08·5 min read

SemiFive Starts Mass Production of HyperAccel Bertha: A >500 mm² 4nm Inference Accelerator

SemiFive starts mass production of HyperAccel's Bertha LLM inference chip on Samsung 4nm. Die area, schedule, contract terms, and the unconfirmed ISA.
ISA Standard2026-09-08

SJTU IPADS SPMP Ratified into RISC-V ISA — First China-Led ISA Extension in RISC-V’s 11-Year History

RISC-V International's Board of Directors approved the SJTU IPADS-led SPMP extension on Aug 31, 2026 — the first ISA extension defined end-to-end by a Chinese team in RISC-V's 11-year history. Deep dive on Supervisor Physical Memory Protection: motivation, encoding, hardware model, deployment on XiangShan and Nuclei.
RISC-V Development2026-09-07·6 min read

Andes Cut a RISC-V LSU Customization From 8.5 Weeks to 6 Using ChipAgents — Here Are the Numbers

Andes used ChipAgents' agentic AI on a RISC-V LSU customization and a BIU verification flow. The reported numbers, and the caveats.
RISC-V Development2026-09-07·6 min read

Design IP Hit $9.45B in 2025: CPU IP Took 43%, and Royalties Outgrew Licensing

SemiWiki's 2025 design IP tally: $9.45B market, CPU IP 43% share, royalties up 16.1% versus licensing up 10.7%. Where RISC-V's opening sits.
RISC-V MCU2026-09-07·6 min read

Haawking HX2000: The RISC-V DSP Line Behind a Fresh Series B — And What Still Isn't Published

Zhongke Haoxin closed a Series B for its Haawking HX2000 RISC-V DSP line. Verified facts, segment context, and the specs still missing.
RISC-V AI2026-09-07·7 min read

RISC-V Matrix Extensions in 2026: IME, VME and AME, Plus the VME Ratification Dates

IME, VME and AME are RISC-V's three matrix tracks. What each does, where they stand, and the VME freeze and ratification dates for 2026.
RISC-V Datacenter2026-09-07·7 min read

YiXing Intelligence Raises ¥1.5B to Scale Its Epoch RISC-V Cloud AI Chip and ELink Superpod

YiXing Intelligence closed a ¥1.5B Series B led by Beijing state funds to mass-produce the Epoch RISC-V cloud AI chip. Verified facts and open gaps.
Software Ecosystem2026-09-05

CPython Officially Adds RISC-V as Tier 3 Platform — First Open ISA in Python’s Support List

CPython now officially supports RISC-V as a PEP 11 Tier 3 platform. RISE Project provides buildbots, PyTorch wheels land on riscv64. Technical deep dive on what Tier 3 means, the roadmap to Tier 2, and the ecosystem gap.
RISC-V MCU2026-09-04·7 min read

Automotive RISC-V Control Chips Get Two Competing Rulebooks: Quintauris RT-Europa and the China SAE Specification

Two automotive RISC-V control-chip specs move in parallel: Quintauris RT-Europa and a China SAE standard covering lockstep, ASIL-D and HSM.
RISC-V AI2026-09-04·8 min read

ESWIN EIC7700 Was the Hardware Behind the HICOOL 2026 RISC-V + AI Challenge — And a 13.3 TOPS vs 19.95 TOPS Discrepancy

ESWIN's EIC7700 board powered the HICOOL 2026 RISC-V+AI final. Here are the verified SoC specs — and why two different TOPS figures are circulating.
RISC-V Development2026-09-04·9 min read

SpacemiT K1 and K3: What Landed Upstream in August 2026 — Kernel, Triton, llama.cpp and Toolchain

SpacemiT August 2026 upstream report: K3 display, UFS and PCIe patches in review, Triton merged into FlagTree, glibc 2.44 and GDB 17.2.
SpacemiT K12026-09-04

SpacemiT K1 Runs ONNX Runtime int4 LLM via IME Matrix Extension

SpacemiT K1 achieves ~80ms/token int4 LLM inference with ONNX Runtime by leveraging the X60 core's IME matrix extension. Technical deep dive on MatMulNBits, quantization, and performance tuning.
RISC-V2026-09-03·12 min read

Lingxu Smart P100: China's First Dynamic SMT4 RISC-V Server CPU

Lingxu Smart P100 is China's first server-class dynamic SMT4 RISC-V CPU core, engineered for the agentic-AI era. Deep dive into SMT1->SMT4 dynamic switching, 20-stage OoO pipeline, 8-decode/10-issue, TAGE branch prediction, SPEC CPU2006, hardware RAS auto-recovery, test chip tape-out Aug 2026.
RISC-V AI2026-09-02·5 min read

Axelera AI Europa: 629 TOPS at 45 W with 16 RISC-V Vector Cores on Samsung Foundry FinFET

Axelera AI's Europa pairs eight 2nd-gen AI PUs with 16 RISC-V vector cores: 629 TOPS at 45 W, 128 MB L2 SRAM, on Samsung Foundry FinFET.
RISC-V AI2026-09-02·5 min read

DeepComputing DC-ROMA RISC-V Mainboard III Enters Production: SpacemiT K3, 60 TOPS, First RVA23 Laptop Board

DeepComputing's DC-ROMA RISC-V Mainboard III enters production on SpacemiT K3 with 60 TOPS, claiming the first RVA23 laptop mainboard.
RISC-V Development2026-09-02·5 min read

Micro Magic MagicV: A 5 GHz, 13,000 CoreMark 64-bit RISC-V Core Running Linux, Zephyr and FreeRTOS

Micro Magic's MagicV 64-bit RISC-V cores claim 5 GHz and 13,000 CoreMarks, 200 mW per core, with Linux, Zephyr and FreeRTOS support.
RISC-V Development2026-09-02·6 min read

openKylin 3.0 Moves to Linux 7.0 with RVA23 Support: 36.5x FP16 Inference Gain from RVV Optimisation

openKylin 3.0 moves to Linux 7.0 with GCC 15, glibc 2.42 and LLVM 22, adds RVA23, and reports 2-5x FP32, up to 36.5x FP16 RVV gains.
RISC-V MCU2026-09-02·5 min read

Qualcomm Dragonwing Q-2390 and IQ-2390: A Real-Time RISC-V MCU Inside a Mainstream IoT SoC

Qualcomm's Q-2390 and IQ-2390 pair a quad-core Kryo CPU and Adreno 704 GPU with a real-time RISC-V MCU, running Linux, Android and Zephyr.
Computational Memory2026-08-31

XCENA MX1: 3,072 RISC-V Cores on a CXL Computational-Memory Card

Deep dive into the XCENA MX1 computational-memory device: 3,072 RISC-V cores, Samsung 4nm, 2TB DDR5, CXL 3.2, vector search and near-data processing. Hot Chips 2026 analysis.
Wireless MCU2026-08-29·12 min read

GigaDevice GD32VW553: RISC-V Dual-Mode Wi-Fi 6 + BLE 5.2 MCU

GigaDevice GD32VW553 is a Nuclei N307 32-bit RISC-V wireless MCU with integrated 2.4 GHz Wi-Fi 6 (802.11ax OFDMA + MU-MIMO) and Bluetooth LE 5.2 radio, 4 MB Flash, 320 KB SRAM, hardware AES/DES/Hash/PKCAU/TRNG, Matter-over-Wi-Fi certified. QFN32/QFN40, -40 to 105 °C.
Automotive RISC-V2026-08-28·14 min read

GigaDevice CCRC4XXX: First Post-Quantum RISC-V Automotive AI MCU

GigaDevice CCRC4XXX automotive AI MCU pairs CRV6 RISC-V cores with native post-quantum crypto (PQC), on-chip NPU, and Evita-Full HSM. Full spec deep-dive plus China's first RISC-V vehicle-control-chip standard from the Suzhou Automotive Summit.
Industrial Edge AI2026-08-27·10 min read

Zhongda Tech K3 Industrial Edge AI Module: 60 TOPS RISC-V on Mini COM-E

Zhongda Tech's SpacemiT K3-based industrial edge AI module delivers 60 TOPS in a Mini COM-E form factor. 8 X100 cores, 8 A100 AI cores, 30B LLM inference, -40 to 70°C, all-domestic supply chain.
RISC-V Datacenter2026-08-25·15 min read

SiFive BigSky SF-2U870: First Rackable 2U RISC-V Datacenter Server

SiFive BigSky SF-2U870 is the world's first enterprise-grade rackable 2U RISC-V server. Deep dive into P870-D cores, DDR5-5600, PCIe Gen5, NVMe, and CUDA/NVLink Fusion support.
WCH MCU2026-08-22·10 min read

CH32X035: All-in-One USB + Type-C PD RISC-V MCU from WCH

WCH's CH32X035 is the first QingKe RV32IMAC MCU with integrated USB 2.0 + USB PD + Type-C PHY, PIOC programmable I/O controller, dual OPA, triple CMP, 12-bit ADC and 65 KB Flash — collapsing any external PD trigger chip.
Development Tools2026-08-20·12 min read

Andes RVBuilder: AI-Assisted RISC-V IDE for VS Code

Andes RVBuilder brings RISC-V toolchain management, debugging and MCP-based AI assistance into Visual Studio Code. Cross-platform for Windows and Linux.
RISC-V IP2026-08-19·17 min read

StarFive Dubhe-100: First Deliverable Server-Grade RISC-V HPC CPU IP
RISC-V Connectivity2026-08-18·15 min read

Timesintelli PT153S: Fully Domestic RISC-V Gigabit USB Ethernet Controller

Technical deep dive into Timesintelli PT153S, a fully-domesticated RISC-V (RV32IMAC) USB 3.2 Gen1 to Gigabit Ethernet controller chip that shipped over 1M units in three months.
HPMicro HPM53M12026-08-17·14 min read

HPMicro HPM53M1: RISC-V MCU for Robot Joint Control

Technical deep dive into HPMicro HPM53M1, a 480MHz RISC-V MCU with integrated 150V motor drivers, 4x CAN-FD, and 2MSPS ADC designed for robot joint servo control.
SpacemiT K3 Hardware2026-08-15·12 min read

SpacemiT K3 Pico-ITX: Compact 60 TOPS RISC-V AI Computer

Technical overview of SpacemiT K3 Pico-ITX, a 2.5-inch Pico-ITX plus SBC built around the 60 TOPS RVA23 K3 AI CPU with 10GbE, NVMe, and dual M.2 expansion.
SpacemiT K32026-08-14·16 min read

SpacemiT K3: Flagship RISC-V AI CPU Deep Dive

Technical deep dive into SpacemiT K3, the world's first RVA23 mass-production RISC-V AI CPU: X100 cores, A100 AI engines, 60 TOPS, and four claimed world-first features.
SpacemiT K1 Application2026-08-13·10 min read

myCobot 280 RISC-V: World's First RISC-V Full-Stack Open-Source Robot Arm

Deep dive into the myCobot 280 RISC-V, the world's first 6-axis collaborative robot arm powered by the SpacemiT K1 RISC-V AI CPU with full-stack open-source design.
RISC-V Ecosystem2026-08-12·12 min read

XiangShan + Ruyi: China's Open RISC-V Processor System and Native OS

Deep dive into XiangShan Kunming Lake open-source RISC-V processor and the Ruyi native operating system for RISC-V.
WCH High-Performance MCU2026-08-11·15 min read

CH32H417: WCH's Dual-Core 400MHz RISC-V MCU with USB 3.0 5Gbps
RISC-V AI Chip2026-08-10·14 min read

中科通量金刚GC3: RISC-V + Dataflow Architecture for Video AIGC

Deep dive into the 金刚GC3 chip by 中科通量: 12 RISC-V cores, 200 TOPS INT8, 128GB LPDDR5 ECC unified memory, dataflow architecture designed for video generation and understanding.
RISC-V IP2026-08-09·16 min read

SiFive Performance P570 Gen 3: Data-Center-Grade RISC-V IP
WCH MCU2026-08-08·13 min read

CH32V407/467: 200MHz RISC-V with Dual USB HS, Ethernet PHY, and RVV
WCH MCU2026-07-15·8 min read

CH32V003: The $0.1 RISC-V MCU Getting Started Guide
WCH MCU2026-07-10·12 min read

CH32V317 Deep Dive: USB 2.0 HS + Ethernet PHY on a Single RISC-V Chip
SpacemiT K12026-07-05·15 min read

SpacemiT K1 OpenWrt SDK: Complete Development Guide
SpacemiT K32026-07-01·18 min read

K3 RVA23 Architecture: Why It Matters for RISC-V
WCH Tools2026-06-25·10 min read

MounRiver Studio: The IDE for WCH RISC-V Development
SpacemiT K12026-06-20·14 min read

K1 AI SDK: Running ML Models on RISC-V Hardware
Industry2026-06-15·16 min read

RISC-V vs ARM in 2026: The Real Ecosystem Gap
WCH MCU2026-06-10·11 min read

Building an Industrial Gateway with CH32V307
Enterprise Software8 min read

Canonical Sets Enterprise Target for Open-Source RISC-V — Ubuntu at Hot Chips 2026

Canonical outlines Ubuntu's enterprise RISC-V strategy at Hot Chips 2026: RVA23 baseline, 95% package parity, native builders, Kubernetes/MicroCloud porting, and RISE Project collaboration.
AI Infrastructure

Epic Semi Contrail AIX: First RISC-V “AI Execution Platform” with 32 Cores + 75 TOPS

Deep dive into Epic Semi Contrail AIX: 32 server-class RISC-V scalar cores + 16 integrated AI cores, up to 75 TOPS (INT8), RVA23, RVV 1.0 + VME, DDR5-6400, PCIe Gen5, CXL 2.0, hypervisor + AIA 1.0. Built for the Agentic AI Era.
Physical AI7 min read

MIPS Launches Acies, Actus & Aegis — Three RISC-V Platforms for Physical AI

GlobalFoundries-owned MIPS unveils three workload-native RISC-V platforms for physical AI: Acies for edge inference, Actus for real-time control, Aegis for safety-critical systems. Software-first design with class-leading tokens-per-watt.
Datacenter

NVIDIA Defines RISC-V as Third Server CPU for CUDA & NVLink Fusion at Hot Chips 2026

At Hot Chips 2026, NVIDIA laid out concrete requirements for RISC-V host CPUs to join its CUDA and NVLink Fusion stacks. RVA23, Boot & Runtime Services, ACPI 6.6, PCIe coherence, and peer-to-peer are mandatory. SiFive named as first RISC-V NVLink Fusion CPU partner.
Physical AI10 min read

Ruixin High-Beam D35: World's First RISC-V Dataflow Physical AI Chip Enters Mass Production

Suzhou Ruixin launches High-Beam D35, the world's first mass-produced RISC-V dataflow architecture physical AI chip. 128 GB memory, self-developed RISC-V CPU core recognized by Intel, ISCA 2026 best paper nominee. Technical deep dive on dataflow computing, physical AI applications, and ecosystem strategy.

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