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From $0.1 MCU
to 60 TOPS AI SoC

The most complete RISC-V product portfolio. WCH QingKe MCUs from ultra-low-cost to industrial connectivity, SpacemiT K1 edge computing SoC, and K3 AI CPU with 60 TOPS. Hardware, software, and value-added services — all on open silicon.

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$0.1
Entry MCU
130K
DMIPS (K3)
7+
RISC-V Chips
10yr
Supply Commitment
Why RISC-V

Why RISC-V for Production Hardware

Proprietary ISAs put one vendor in control of the roadmap, the pricing, and what you are allowed to inspect. RISC-V is an open standard with a frozen base specification — auditable, and second-sourcable.

🔓

No Vendor Lock-in

RISC-V is an open, royalty-free ISA implemented by many silicon vendors. Second-sourcing does not require a firmware rewrite, so your roadmap is not tied to a single supplier.

🛡

Multi-Source Supply

The same ISA is produced by vendors across multiple regions. When lead times or allocation shift, you can qualify an alternate part without rebuilding your software stack.

🔍

Fully Auditable

Every instruction is publicly specified and reviewable. No undocumented modes, no hidden microcode — security review and certification work against a published specification.

⚡

Custom Extensions

Add domain-specific instructions for AI, crypto, or real-time. ARM doesn't let you modify the ISA — RISC-V does.

🌍

Long-Term Availability

A vendor-neutral ISA with a frozen base specification, maintained by RISC-V International. Silicon roadmaps outlive individual vendor product lines — suitable for 10-year lifecycle programs.

🚀

Ecosystem Growth

25% global processor market share in 2026. 69 billion RISC-V cores shipped. Production-ready.

Product Roadmap

Full Spectrum RISC-V Product Path

From ultra-low-cost MCUs to 60 TOPS AI SoCs. One architecture, seven tiers, infinite possibilities.

Tier 1
CH32V003
QingKe V2A · 48MHz
$0.1
→
Tier 2
CH32V208
QingKe V4C · 144MHz
$1
→
Tier 3
CH32V307
QingKe V4F · 144MHz
$3
→
Tier 4
CH32V317
QingKe V4F · 144MHz
$4
→
Tier 5
CH32H417
Dual-core · USB 3.0
$6
→
Tier 6
K1-8G
8x X60 · 1.6GHz
$99+
→
Tier 7
K3
8x X100 + 8x A100 · 60 TOPS
$299+
WCH MCU Family

QingKe RISC-V Microcontrollers

WCH (Nanjing Qinheng) self-designed RISC-V cores. From the world's cheapest RISC-V MCU to industrial chips with Ethernet, CAN, BLE, and USB 3.0.

CH32V RISC-V MCU development board
CH32V003
Ultra-Low Cost
The world's most affordable RISC-V MCU. 48MHz QingKe V2A with USB and 2.4G RF. Replaces STM32F0 at a fraction of the cost.
Core
QingKe V2A (RV32EC)
Clock
48 MHz
Flash/RAM
16KB / 2KB
Package
SOP-8 / QFN-20
USB 2.0 FS2.4G RFTouch KeyADCUSARTI2CSPI
$0.10
IoT sensors, education, consumer electronics
CH32V208
Wireless
RISC-V MCU with BLE 5.3 and 10Mbps Ethernet. Perfect for connected IoT devices needing wireless and wired networking.
Core
QingKe V4C (RV32IMAC)
Clock
144 MHz
Flash/RAM
128KB / 64KB
Package
QFN-28/48/68
BLE 5.310M EthernetUSB OTGCANOPA x2USART x4ADC 12-bitTouch Key x10
$1.00
Smart home, wireless sensors, connected appliances
CH32V307
Connectivity
Industrial RISC-V MCU with gigabit Ethernet MAC, 480Mbps USB, dual CAN, 8 UART. Connectivity powerhouse for multi-protocol devices.
Core
QingKe V4F (RV32IMACF)
Clock
144 MHz
Flash/RAM
256KB / 64KB
Package
LQFP-64/100
Gigabit Ethernet MAC10M PHYUSB 2.0 HS 480MbpsCAN x2USART x8DVPFSMCFPU
$3.00
Industrial gateways, multi-protocol devices, network equipment
CH32V317
Latest Interconnect
Latest interconnect MCU with 480Mbps USB PHY and 100M Ethernet PHY. Dual ADC, quad OPA for demanding industrial control.
Core
QingKe V4F (RV32IMACF)
Clock
144 MHz
Flash/RAM
256KB / 64KB
Package
LQFP-100 / QFN-68
480Mbps USB (built-in PHY)100M Ethernet PHYUSART x8OPA x4Dual ADCDual DACCAN x2
$4.00
Network devices, industrial automation, test equipment
CH32H417
USB 3.0 Dual-Core
Dual-core RISC-V MCU with 5Gbps USB 3.0 PHY and 100M Ethernet. First RISC-V chip with integrated USB 3.0.
Core
Dual-core V5F + V3F
Clock
Dual RISC-V
Flash/RAM
High-density
Package
QFN
USB 3.0 SuperSpeed 5Gbps100M Ethernet PHYDual HS ADCDual DACPDUSBUHSIF
$6.00
High-speed USB networking, data acquisition, test instruments
SoC Platform

SpacemiT RISC-V SoCs

From edge networking to AI computing. SpacemiT Key Stone series delivers production-ready RISC-V SoCs with full Linux and OpenWrt support.

K3 AI compute module

K3: RISC-V AI CPU (60 TOPS)

World's first RVA23-compliant RISC-V AI CPU. 8x X100 at 2.4GHz + 8x A100 — 60 TOPS. Runs 30B LLMs locally. Jetson Orin Nano pin-compatible. Ubuntu 26.04 LTS.

AI Computing
60 TOPS AI 30B LLM Local RVA23 Compliant Orin Nano Compatible
Key Specifications
CPU8x X100 @ 2.4GHz (4-issue OoO)
AI Cores8x A100 (60 TOPS)
DMIPS130,000
LLM30B params local (>10 tok/s)
MemoryLPDDR5 up to 32GB (51GB/s)
Ethernet4x GMAC with TSN
PCIe8 lanes Gen3
USB4x USB 3.0 + 1x USB 2.0
Serial17x UART, 10x CAN-FD, 9x I2C
DisplayDual 4K@60 (DSI+DP)
Video4K@180fps dec, 4K@90fps enc
Camera4x MIPI-CSI (12 cam)
SecuritySM2/3/4, AES, SHA, RSA, Secure Boot
VirtualizationRVH 1.0, AIA, IOMMU
OSUbuntu 26.04 LTS, Bianbu OS
TDP15-25W
Temp-40C to 85C
CompatJetson Orin Nano pin-compat
K1 RISC-V development board

K1-8G: RISC-V Edge Gateway SoC

8-core X60 RISC-V at 1.6GHz with PowerVR GPU, 2 TOPS AI, and 8 gigabit Ethernet ports. Production-ready with OpenWrt 23.05.

Edge Computing
Key Specifications
CPU8x X60 RISC-V @ 1.6GHz
DMIPS50,000 (50K DMIPS)
GPUPowerVR BXE-2-32
AI2 TOPS (NPU)
MemoryLPDDR4X up to 16GB
Ethernet2x GMAC (RGMII)
PCIe5x PCIe Gen2
Serial12x UART, 2x CAN-FD
OSOpenWrt 23.05, Linux 6.1
Process22nm
Value-Added Services

Beyond Silicon: Full-Stack RISC-V Services

We don't just sell chips. We deliver complete RISC-V solutions from hardware design to deployment, certification, and long-term support.

How each service works →

📥

Hardware Design

Reference designs and custom PCBs

  • Reference designs for all tiers
  • Custom PCB layout
  • SI/PI simulation
  • Enclosure & thermal design
💻

Software & BSP

Board support packages and firmware

  • OpenWrt BSP for K1/K3
  • Bianbu OS / Ubuntu
  • RT-Thread / bare-metal
  • Driver development
🏭

ODM / OEM

Custom manufacturing and branding

  • Custom board design
  • Brand customization
  • Volume manufacturing
  • Quality control
🛡

Certification

Global compliance assistance

  • CE / FCC / CCC
  • Industrial certifications
  • AEC-Q100 (automotive)
  • EMI/EMC testing
📦

Supply Chain

Long-term supply guarantee

  • 10+ year commitment
  • Inventory management
  • Buffer stock
  • EOL notification
🎓

Technical Support

Engineering support & training

  • Dedicated FAE team
  • On-site training
  • Documentation & wiki
  • Community forum
Use Cases

Where RISC-V Wins

From network infrastructure to industrial automation — four deployments where RISC-V is shipping in production today.

Read the deployment breakdowns →

Network gateway operations Network

Carrier & Campus Network Infrastructure

Network operators need equipment they can audit end to end and keep in service for a decade. RISC-V gateways running OpenWrt give full-stack visibility — bootloader to application — with no opaque binary blobs.

K1-8G with 8x GbE, physical isolation, CAN-FD, OpenWrt
Industrial AI gateway deployment Industrial

Industrial IoT & Automation

Multi-protocol industrial gateways connecting CAN, RS-485, Ethernet, wireless. RISC-V MCUs reduce BOM 60% vs ARM.

CH32V307 + CH32V208, CAN-FD, BLE 5.3, Gigabit Ethernet
AI / Edge

On-Device AI Computing

Run 30B LLMs locally without cloud. Privacy-preserving AI for robotics, smart home, content creation.

K3 with 60 TOPS, 32GB LPDDR5, Orin Nano compatible
Research

Academic & Research Platforms

Open ISA enables full-stack research from RTL to applications. Ideal for university courses and architecture research.

CH32V003 ($0.1) for education, K1/K3 for research
Software

Open Source, Fully Supported

Every product ships with complete open-source software support.

📶

OpenWrt 23.05

Full OpenWrt for K1 with mwan3, nftables, tc

🤖

Ubuntu 26.04 LTS

Canonical officially supports K3. Bianbu OS available

💻

MounRiver Studio

Free IDE for all WCH RISC-V MCUs. Arduino Core support

⚙

RT-Thread

Full RTOS for CH32V with rich driver ecosystem

Tech News

RISC-V Industry News

Latest developments in the RISC-V ecosystem — from chip launches to market analysis.

AI 2026-10-13

SpacemiT K3 Completes DeepSeek Harness Adaptation: a RISC-V Edge Node for Open-Weight LLM Inference

SpacemiT has completed adaptation and run verification of DeepSeek Harness on its K3 AI CPU, making the RVA23-compliant chip (8×X100 app cores at 2.4 GHz + 8×A100 AI cores, ~60 TOPS INT4 sparse) a supported RISC-V edge hardware node for the DeepSeek inference framework. The company also confirmed K3-based motion-control compute was field-tested on the LLong 2.0 humanoid robot with the Beijing Humanoid Robot Innovation Center. K3 ships to overseas customers as SBCs and compute-cluster servers; a full design-documentation release is open.

Qichacha company profile →
Event 2026-10-13

6th RISC-V China Summit Set for October 18–20 in Shenzhen with 3,000+ Attendees and 150 Exhibitors

The 6th RISC-V China Summit opens October 18–20 at the Shenzhen Convention & Exhibition Center (Futian), one of the world’s three major RISC-V summits. Organizers expect 3,000+ on-site attendees, 150 exhibitors and 800k online reach; confirmed participants include Alibaba DAMO Academy (XuanTie), ESWIN Computing, SpacemiT, Lanxin Computing and Tenstorrent. The framing from 21st Century Business Herald: RISC-V now holds roughly 25% of global processor shipments, and competition is shifting from raw performance to ecosystem maturity — OS adaptation, toolchain completeness and industrial-scale case replication.

21st Century Business Herald →
Software 2026-10-09

Ubuntu 26.10 Ships First Official RISC-V Desktop ISO, Promotes SpacemiT K3 Pico-ITX to Supported Hardware

Canonical announced on October 9 that Ubuntu 26.10 “Stonking Stingray” (release October 15) will include the distribution’s first official riscv64 desktop ISO — the same GNOME live installer x86 and Arm users get. The SpacemiT K3 Pico-ITX moves from community-supported to the Ubuntu-supported boards list, after Canonical cherry-picked K3 display patches and built Flutter 3.44.0 for riscv64. Daily images are experimental; an Xubuntu Minimal image is offered for QEMU on Ubuntu 25.10+ hosts. Ubuntu 26.04 LTS does not gain K3 support.

Read the setup guide →
Market 2026-10-09

ESWIN Computing Lists on HKEX: the First Publicly Traded RISC-V Chip Stock Goes Live at ~HK$34 Billion

ESWIN Computing (01256.HK) completed its Main Board listing on October 9, becoming the first RISC-V-architecture chip company to trade publicly. Final offer price HK$1.55 (mid-range of the HK$1.48–1.59 book); grey-market close HK$1.575 (+1.61%). Nine cornerstone investors — including Hefei Jiantou, TFME-affiliated Haiyao, Unisplendour-affiliated Jizhong International, and ORIX — subscribed HK$1.161 billion, nearly half the offering. Press reports put the closing market cap near HK$34 billion. The company (founded by former BOE chairman Wang Dongsheng) spans HMI, embodied-AI interconnect and edge-compute lines; 150+ chips in production, 80+ in development. The listing marks the RISC-V ecosystem’s first major capital-markets validation.

Tencent News →
Software 2026-10-11

RISC-V Kernel Auto-Vectorization Goes Measured at LPC 2026: +15.1% on One Workload, +0.1% Across the System

A Linux Plumbers Conference 2026 session (Oct 6, RISC-V microconference, Prague) put numbers on compiling the RISC-V kernel with auto-vectorization — territory Linux has treated as forbidden, since kernel-mode SIMD is tuned for stack footprint and worst-case latency. Against a -mtune build the spread is wide: LZ4 compression +15.1% on one target but −7.5% on another, Btrfs unlink up to +8.4%, Nginx +0.3% to +2.2%. The honest headline is the system view — one target’s geometric mean across its whole benchmark suite is +0.1%, with hackbench down 2.5–4%. Cost: saving v0–v31 costs 512 B at VLEN 128 and 4 KiB at VLEN 1024, vector sections are restricted in hardirq/NMI, and the big gains require a nonportable per-CPU build.

Read the data breakdown →
Product 2026-10-12

HPMicro Launches HPM5100: a 400 MHz RISC-V Mixed-Signal MCU Driving Four Motors From One Chip

Announced October 12 at the opening day of the China International Industry Fair in Shanghai, HPMicro’s HPM5100 series targets high-end mixed-signal control: a RISC-V core at 400 MHz with 416 KB SRAM and 1 MB Flash, plus an integrated analog chain — four 16-bit ADCs at up to 2 MSPS in 16-bit mode with differential input, four op-amps with configurable gain and four high-speed comparators. Rich motor-PWM resources enable a single-MCU one-to-four motor topology. CEO Zeng Jintao frames it as moving from high-performance MCU to high-performance mixed-signal MCU; target applications are robotics, drones, motor drives and industrial automation.

Sina Finance →
Tech Blog

Technical Resources

Official documentation, application notes, and development guides for WCH QingKe MCUs and SpacemiT K-series SoCs.

RISC-V Development 9 min

RISC-V Kernel Auto-Vectorization at LPC 2026: the 15% Headline, and What the Slides Actually Measured

A close reading of the LPC 2026 RISC-V session Optimizing the kernel with vector. Against a -mtune build the results are workload-specific: LZ4 compression +15.1% on one target but −7.5% on another, Btrfs unlink +8.4%, XFS on one target “not significant”, Nginx +0.3% to +2.2%. One target’s geometric mean across its entire system-benchmark suite is +0.1%, with hackbench down 2.5–4%. Includes both data tables verbatim, the separate per-CPU-tuned comparison (+4.98% geomean), the real cost — 512 B vs 4 KiB of saved vector state, hardirq/NMI restrictions — and why prctl(PR_RISCV_V_*) is not this switch. No invented figures; inferences flagged.

RVVauto-vectorizationLPC 2026Linux kernelbenchmarks
2026-10-13
RISC-V Datacenter 4 min

SpacemiT K1 and K3 Devicetrees for Linux 7.4: CPU Scaling, CTF2301 Fan Control and the CLINT-to-ACLINT Fix

Yixun Lan’s spacemit-dt-for-7.4-1 pull (Oct 7; 14 files, +571/−56, 28 commits from 12 contributors) is the most consequential SpacemiT devicetree drop in several cycles: the K3’s wrong SiFive CLINT node is replaced with real T-Head C900 ACLINT nodes (k3.dtsi +229 lines), CTF2301 thermal and fan control lands on the CoM260, CPU scaling arrives per-board for Muse Pi Pro / Orange Pi R2S / RV2, and Pico-ITX gains USB3 B/C plus rfkill. K1 boards get an EEPROM-sourced Ethernet MAC. Not merged; no frequencies or OPP tables are stated anywhere.

devicetreeACLINTcpufreqthermalLinux kernel
2026-10-09
RISC-V Development 8 min

An SBI Watchdog for RISC-V: Firmware-Defined Driver With IMSIC Pretimeout (RFC)

Prajwal N posted an RFC two-patch series (Oct 2, Copyright Qualcomm Inc.) adding a 406-line SBI watchdog driver: watchdog ops map onto six SBI_EXT_WDT ecalls (START, STOP, PAT, READ/WRITE ATTRIBUTE, WRITE_NOTIF_MSI_MESSAGE) with a 60 s default timeout, and the pretimeout arrives as an IMSIC platform MSI that OpenSBI itself raises — no wired interrupt, no MMIO block, no device-tree node. Loading is gated on SBI 3.0+ plus a positive extension probe. Not merged; no hardware platform or OpenSBI implementation is named yet.

SBIwatchdogIMSICMSILinux kernel
2026-10-08
RISC-V Development 8 min

gtrace: RISC-V Hardware Trace Heads for Mainline Linux With 14-Patch v6 Series

Mayuresh Chitale posted v6 (Oct 1) of a 14-patch series adding gtrace — an architecture-neutral hardware-trace framework whose first backend is the ratified RISC-V E-trace spec. 24 files, +3,160 lines: an 858-line core, encoder and RAM-sink drivers, a gtrace perf driver with its own PMU, tools/perf support and a new DT binding. Drivers are protocol-agnostic (E-trace and N-trace); v6 adds cycle detection and serialized start/stop. Tested via a QEMU model and perf record -e gtrace/event=0x1/. Not merged — with the cover letter flagging future Arm components on the same framework.

gtraceE-traceperfLinux kernelTracing
2026-10-04
RISC-V Virtualization 6 min

RISC-V IOMMU v6: IMSIC MSI Remapping Turns On IOMMU_DMA and VFIO Device Assignment

Andrew Jones' v6 series (Sep 25; 13 patches from Jones, 3 from Tomasz Jeznach; 22 files, +646/−127) adds IMSIC MSI remapping so a device's MSI target address is translated like its DMA — enabling IOMMU_DMA, VFIO type1 and KVM_VFIO on 64-bit RISC-V. The v5/v6 design maps every possible IMSIC page into one contiguous IOVA range and reduces target-CPU selection to arithmetic. Two stated gaps: no MSI data validation in the RISC-V IOMMU spec (allow_unsafe_interrupts=1 needed) and no irqbypass yet. Not merged.

IOMMUIMSICVFIOKVMiommufd
2026-10-04
RISC-V Development 7 min

Linux RISC-V TLB Flush Path Tracepoint Reaches v2: Local, SBI RFENCE or Cross-CPU Call

Roman 'Hedin' Storozhenko posts v2 of a Linux RISC-V patch that adds riscv_tlb:riscv_tlb_flush_path to expose whether the kernel handles TLB invalidation locally, via SBI RFENCE, or through a cross-CPU call. Includes field table, scope/path semantics, ftrace/perf usage, and the review note that Jisheng Zhang asked for a concrete use case before accepting.

RISC-VLinux kernelTLBtracepointSBI RFENCE
2026-10-03
Virtualization 9 min

KVM on the SpacemiT K3 Reaches Stock Distros: Ubuntu 26.10 Hands-On, a Fedora Com260 Wiki, and Why the BSDs Cannot Boot

Three independent teams now run virtualization on SpacemiT K3 silicon: Xen (Vates/ISCAS, Sep 29), KVM on Ubuntu 26.10 mainline 7.3.0 (Debian 13 riscv64 guest under -cpu host, zvk* vector-crypto extensions, 2.37 GB/s AES-GCM), and a Fedora KVM bring-up wiki for the Com260 board reviewed by Red Hat on Oct 1. The deep dive covers what the guest inherits, the M-mode firmware trap, and the one bug nobody should rediscover: K3 firmware leaves mcounteren.CY/IR clear, so rdcycle/rdinstret raise SIGILL and kill all three BSDs (FreeBSD 15.1 panics at 0xc0002573). Plus the five mainline gaps: dead UFS, invisible A100 cluster, 13.4% compile regression, and no power management.

KVMUbuntu 26.10FedoraSpacemiT K3rdcycle
2026-10-02
RISC-V Development 8 min

SpacemiT K3 PCIe Root Complex Heads for Upstream Linux: v7 Patch Series

Inochi Amaoto's v7 patch series adds PCIe RC controller support for the SpacemiT K3 to upstream Linux by generalizing the existing K1 DesignWare PCIe driver. The K3 controller uses an external IMSIC MSI controller (RISC-V AIA) and multiple PHYs, so the refactor adds device-data support, multiple PHY handles, a device-ID helper, and K3-specific init logic. v7 keeps PERST# asserted on init failure and disables ASPM L1 as a workaround. Tested-by Aurelien Jarno; review from Andy Shevchenko. Not yet merged.

SpacemiTK3PCIeLinuxIMSIC
2026-10-01
Virtualization 8 min

Xen Boots on the SpacemiT K3: the First RVA23-Compliant RISC-V Board With APLIC, IMSIC and the H-Extension

The two-step story of Xen on real RISC-V silicon, annotated: first a HiFive Premier P550 whose 2021-era EIC7700X core implements hypervisor-extension draft v0.6 (forcing the port to gate pre-ratification CSRs, with CI wired over TFTP and UART), then the SpacemiT K3 — the only board on the market shipping both APLIC/IMSIC and the ratified H-extension. ISCAS's Zheng Zhang drove the K3 port with Vates; announced at Xen Summit 2026 in Munich; the roadmap points at a K3 node in the project's CI. With the AIA/H-extension virtualization context and the hardware checklist for anyone porting Xen to RISC-V.

XenSpacemiT K3RVA23APLICH-Extension
2026-09-30
RISC-V HPC 11 min

Teaching OpenBLAS About the K3's VLEN=1024 AI Cores: HPL on a Heterogeneous RISC-V SoC

The opensolvers team added a RISCV64_ZVL1024B target to OpenBLAS and ran HPL on the SpacemiT K3's A100 AI cores: 15 → 35.9 GFLOP/s on the A100 cluster, and an equal 8+8 X100+A100 mix reaching 57.5 GFLOP/s — beating the X100-only baseline of 53.2. Annotated with the /proc/set_ai_thread affinity mechanism, the VLEN-migration SIGSEGV pitfall, and the kernel-geometry rule that performance follows kernels, not register width.

SpacemiTK3OpenBLASHPLVLEN=1024
2026-09-29
Capital Markets 8 min

ESWIN Computing Passes HKEX Listing Hearing — the Path to the First Publicly Listed RISC-V Chip Company

Beijing ESWIN Computing passed the HKEX Main Board hearing on Sep 21, 2026, positioning it to become the first publicly listed RISC-V-architecture chip company. Full prospectus-coverage breakdown: revenue ¥1.752B → ¥2.431B (2023–2025), Q1 2026 ¥494M (+18.4% YoY), compute products jumping from ¥375K to 45% of quarterly revenue in three years, Frost & Sullivan market sizing, and the honest risk register — customer concentration, margins, foundry dependence.

ESWINHKEXIPOCapital MarketsEcosystem
2026-09-23
ISA & Software 11 min

After RVA23: CFI, the Three Matrix Extension Routes, and What RVA23.1 Adds — Canonical's Distro View

Canonical's Jon Taylor maps the post-RVA23 ISA landscape: Zicfilp/Zicfiss control-flow integrity (landing pads, shadow stacks, and the Zimop trap caveat), the three matrix routes VME/IME/AME and their OS context-switch costs, runtime discovery via sys_riscv_hwprobe(), and the RVA23.1 development options that matter for distros — Ssdbltrap, Sscfg, Ssctr for PGO. Annotated with official spec links and cross-referenced with our K3 IME and NVIDIA VME coverage.

CanonicalRVA23CFIIMEVME
2026-09-22
RISC-V AI 10 min

Ruixin Gaoguang D35: A RISC-V Dataflow Physical-AI Chip with 128 GB VRAM and >90% Compute Utilization

Suzhou Ruixin's Gaoguang D35 entered mass production in June 2026: a fully self-developed RISC-V CPU core paired with a dedicated LPU dataflow processing unit, 128 GB on-chip VRAM, Chiplet advanced packaging, and a claimed >90% compute utilization. ISCA 2026 best-paper nomination. Qiyuan Robot partnership announced Sep 20. Five target scenarios: smart security, industrial inspection, embodied robots, autonomous driving, smart storage.

RuixinDataflowLPUChipletEdge AI
2026-09-21
RISC-V AI 12 min

Inside the SpacemiT K3 Preview Paper: Homogeneous Fusion, X100 + A100, and What 60 TOPS Actually Means

SpacemiT’s official K3 preprint (2026-01-29) annotated: X100 (OpenC910 lineage, TAGE, 17-cycle L2 hit, 7 VMs/core) and A100 (VLEN 1024, IME 1.0/2.0 matrix tiers, shared Tensor Core closed at 2.1 GHz), one SMP Linux with AI-partitioned cores, the ONNX Runtime + Triton stack, and every published benchmark table — SPEC CINT2006 22.88, −5.48% under KVM, GHASH 46.6×, 3.28× memory bandwidth. All figures vendor-published and labeled.

SpacemiTK3X100A100IME
2026-09-20
RISC-V Datacenter 11 min

First Mass-Produced RISC-V AI Supernode Goes Live: EVAS Epoch in an Operator Data Center

EVAS Intelligence's 64-node supernode — Epoch chips on E200-L liquid-cooled OAM modules in an orthogonal backplane-free ELink fabric — is now serving MoE traffic in a Shijiazhuang operator data center, backed by a new ~RMB 2B round at a ~RMB 15B valuation. Full deployment tables, MoE expert-routing mechanics, the gen-2 roadmap, and a strict vendor-claims vs verified-facts separation.

EVASEpochSupernodeELinkMoE
2026-09-19
Dev Tools 9 min

Andes AX66 Pre-Silicon: Linux KVM + Dual LLM Inference on FPGA Before Tape-Out

S2C mapped a quad-core AndesCore AX66 cluster (13-stage OoO, RVA23, RVH + AIA, CHI) onto a single AMD Versal Premium VP1902 in the Prodigy S8-100: 60 MHz, ~55% logic, Linux KVM with two VMs, and two TinyStories-42M LLMs running pre-silicon. Full AX66 spec tables from the official product page, what each demo layer exercises, and a bring-up checklist for RVA23 SoC teams adding custom extensions.

AndesAX66S2CFPGAKVM
2026-09-18
RISC-V AI 11 min

MNN LLM Inference on SpacemiT K3 — IME2 W4B64 Quantization and Benchmarks

Alibaba MNN on SpacemiT K3: IME2 matrix extension, asymmetric W4B64 quantization, TCM double-buffer pipelining; Qwen3-0.6B hits 381 tok/s prefill, 54.49 tok/s decode. Build flag, benchmark commands and source-code map for running local LLMs on K3's A100 AI cores.

SpacemiTK3MNNIME2LLM
2026-09-17
Datacenter 9 min

SiFive + AMD ROCm on BigSky — RISC-V Head Node Gets Its Second GPU Stack

AMD ROCm 10.0 demoed on the BigSky SF-2U870 (32× P870-D head node + Radeon AI PRO R9700) running Gemma4-E2B at AI Infra Summit 2026. Full BigSky hardware spec tables, the ROCm demo software stack, and how the AMD path compares with NVIDIA’s CUDA port — plus what a RISC-V head node means for AI infrastructure economics.

SiFiveAMDROCmBigSkyP870-D
2026-09-16
Automotive 9 min

Infineon Maps RISC-V for Automotive Zone Controllers at Hot Chips 2026 — MCU Island + MPU Island

Infineon’s Hot Chips 2026 automotive talk consolidated: the domain → zonal → central-compute E/E transition, Path A vs Path B zone controllers, MCU island + MPU island super-integration, RVI AUTO-SIG profiles (RV32E+I+M+U baseline), RVM virtualization for mixed criticality, and the three-architecture AURIX portfolio (TriCore + Arm + RISC-V). Full tables: workload timing spread, profile contents, and the ecosystem checklist.

InfineonZone ControllerAUTO-SIGRVMAURIX
2026-09-15
Compliance 11 min

EU Cyber Resilience Act Article 14 — 24-Hour Vulnerability Reporting Hits RISC-V IoT

EU CRA Article 14 went live on Sept 11, 2026 with a 24-hour early-warning clock for actively exploited vulnerabilities on every product with digital elements sold in the EU. This deep-dive walks RISC-V MCU & SoC vendors through scope, the 24/72/14-day reporting workflow via ENISA’s Single Reporting Platform, the €15M / 2.5% global-turnover penalty tier, the SBOM and security-by-design obligations that take full effect on Dec 11 2027, and a five-step engineering checklist VDP → SBOM → Annex VII file → conformity assessment → CE mark.

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CPU IP 8 min

Nuclei Tech (芯来科技) IPO — Global First ASIL-D RISC-V Automotive CPU IP

China’s earliest RISC-V CPU IP company files for BSE listing. NA900 is the world’s first RISC-V CPU IP certified to ISO 26262 ASIL-D. UX1030H targets RVA23 high-performance scenarios. 300+ customers, 87% gross margin, 4.85B cash, zero debt.

ASIL-DNA900UX1030HRVA23IPO
2026-09-12
Software Ecosystem 10 min

Rust on RISC-V 2026 — Tier 2 with Host Tools + the New riscv64a23 Target

A snapshot of Rust’s RISC-V platform support as of September 2026: which targets are stable, which is new, and why the Tier 1 promotion RFC has been open since October 2024. Companion to the CPython Tier 3 article.

Rustriscv64a23Tier 2RISESpacemiT K3
2026-09-12
Datacenter 11 min

RISC-V Server Chips Enter Production Datacenter — LX500, K3 & JH-B100

Three RISC-V server chips from the 5th Dishui Lake Forum cover compute, AI acceleration, and BMC management. Deep dive into BlueChip LX500, SpacemiT K3, and StarFive JH-B100.

LX500K3JH-B100Datacenter
2026-09-11
ISA Standard 9 min

SJTU IPADS SPMP Ratified into RISC-V ISA — First China-Led ISA Extension in RISC-V’s 11-Year History

RISC-V International’s Board approved the SJTU IPADS-led SPMP (Supervisor Physical Memory Protection) extension on Aug 31, 2026 after a seven-year campaign. SPMP replaces page-table walks with a small CSR “sticky-note” file for one-cycle physical-address range checks on M-mode and S-mode accesses. Shipping in XiangShan and Nuclei UX10/UX10B silicon; first ISA feature ever defined end-to-end by a Chinese team.

SPMPSJTU IPADSTEEXiangShan
2026-09-08
Physical AI 10 min

Ruixin High-Beam D35 — World’s First RISC-V Dataflow Physical AI Chip

Suzhou Ruixin launches the first mass-produced RISC-V dataflow architecture physical AI chip. 128 GB memory, self-developed RISC-V CPU core recognized by Intel, ISCA 2026 best paper nominee. Dataflow computing eliminates program counters for deterministic low-latency inference in industrial intelligence, embodied AI, cockpit-driving integration, and 5G/AI-RAN communications.

DataflowRISC-VPhysical AIISCA 2026
2026-09-09
Enterprise 8 min

Canonical Sets Enterprise Target for Open-Source RISC-V

Canonical at Hot Chips 2026: RVA23 baseline from Ubuntu 25.10, ~95% package parity with amd64, 55.1% test pass rate, Kubernetes/MicroCloud porting, and native RISC-V build farm on Scaleway with Alibaba and SpacemiT hardware.

UbuntuRVA23KubernetesRISE
2026-09-08
Physical AI 7 min

MIPS Launches Acies, Actus & Aegis — Three RISC-V Platforms for Physical AI

GlobalFoundries-owned MIPS unveils three workload-native platforms: Acies for edge AI inference (open NPU), Actus for real-time embedded control (motion, sensor fusion), Aegis for mission-critical safety systems. Software-first design with class-leading tokens-per-watt. AMD and MediaTek endorse open-standard RISC-V.

MIPSGlobalFoundriesPhysical AIRISC-V
2026-09-06
Software 8 min

CPython Officially Adds RISC-V as Tier 3 Platform — First Open ISA in Python’s Support List

CPython core developer Stan Ulbrych announced riscv64-unknown-linux-gnu as a PEP 11 Tier 3 platform. RISE Project provided real hardware buildbots. RISC-V is the only fully open ISA in CPython’s official support tiers. PyTorch 2.13.0 riscv64 wheels already land; 99.998% test-suite pass rate. Roadmap: pre-merge CI, then Tier 2 promotion.

CPythonPEP 11RISETier 3
2026-09-05
SpacemiT K1 10 min

SpacemiT K1 Runs ONNX Runtime int4 LLM via IME Matrix Extension

Community benchmarks show the K1's X60 core achieving ~80 ms/token for Qwen2.5-0.5B in int4 format through ONNX Runtime, leveraging the IME (Integrated Matrix Extension) for MatMulNBits acceleration. A technical deep dive on RVV+IME kernel porting, block-wise quantization, and what this means for edge AI on RISC-V.

K1ONNX RuntimeIMEint4
2026-09-04
Server CPU 12 min

Lingxu Smart P100: China’s First Dynamic SMT4 RISC-V Server CPU, Built for Agentic AI

P100 is the first domestic dynamic SMT4 server-grade RISC-V CPU core: SMT1→SMT4 runtime switching with zero reboot, 20+ stage out-of-order pipeline, 8-decode / 10-issue superwide, TAGE branch prediction, >20/GHz single-core (SPEC CPU2006), hardware RAS auto-recovery. Test chip taped out Aug 2026 on domestic node; 128-core CPU 2027, MP 2028. Backed by Biren and other domestic GPU vendors for CPU+GPU co-design. Decode the microarchitecture, RAS strategy, agentic-AI workload modeling, and ecosystem implications.

Lingxu SmartP100SMT4Agentic AI
2026-09-03
Datacenter 10 min

NVIDIA Defines RISC-V as Third Server CPU for CUDA & NVLink Fusion at Hot Chips 2026

NVIDIA published the exact platform contract a RISC-V host CPU must meet: RVA23, Boot & Runtime Services, ACPI 6.6, PCIe I/O coherence, and peer-to-peer. NVLink Fusion adds a ~88-lane C2C interconnect with CHI coherence, DOCA, and NCCL. SiFive named as first RISC-V NVLink Fusion CPU partner. Vera Rubin NVL72 rack shows the target architecture. Two generations to viable third server-CPU option.

NVIDIACUDANVLink FusionSiFive
2026-09-02
AI Infrastructure 11 min

Epic Semi Contrail AIX: First RISC-V “AI Execution Platform” with 32 Cores + 75 TOPS

32 server-class RISC-V cores + 16 integrated AI cores on the Contrail Compute 5000 Series, RVA23-compliant, RVV 1.0 + VME matrix extension, 4-channel DDR5-6400 up to 1 TB, 64-lane PCIe Gen5, CXL 2.0, RISC-V Hypervisor + IOMMU + AIA 1.0. Designed for the inference + RAG + agentic-AI era, not training. Full architecture, software stack, and reference server configuration.

Epic SemiContrail AIXVME75 TOPS
2026-09-01
Computational Memory 13 min

XCENA MX1: 3,072 RISC-V Cores on a CXL Computational-Memory Card

Samsung 4 nm, 2 TB DDR5 + SSD-backed "Infinite Memory", PCIe 6 / CXL 3.2 x8 at 128 GB/s. 24 independent 128-core subsystems running at 1.1 GHz deliver ~3 TFLOPS for vector search, KV-cache, and near-data processing. Deep dive into the Hot Chips 2026 architecture, software stack (C/C++/Rust + Parallel Xceleration Library), and rack-scale reference design.

XCENA3072 coresCXL 3.2Samsung 4nm
2026-08-31
Wireless MCU 12 min

GigaDevice GD32VW553: RISC-V Dual-Mode Wi-Fi 6 + BLE 5.2 MCU for Matter IoT

Nuclei N307 RISC-V core @ 160 MHz, integrated 2.4 GHz Wi-Fi 6 (802.11ax OFDMA + MU-MIMO) + BLE 5.2 radio with shared 2.4 GHz path, up to 4 MB Flash, 320 KB SRAM, hardware AES/DES/Hash/PKCAU/TRNG, Matter-over-Wi-Fi certified. QFN32/QFN40, -40 to 105 °C.

GD32VW553Wi-Fi 6BLE 5.2Matter
2026-08-29
Automotive RISC-V 14 min

GigaDevice CCRC4XXX: First Post-Quantum RISC-V Automotive AI MCU

China’s first systematic RISC-V vehicle-control-chip standard launched at the Suzhou Automotive Summit. Headlining chip: CRV6 RISC-V + 0.3 TOPS NPU + ASIL-D + native PQC (ML-KEM/ML-DSA). Targets Infineon TC4Dx, Renesas U2A in central-domain and ADAS controllers.

CCRC4XXXCRV6PQCASIL-D
2026-08-28
Industrial Edge AI 10 min

Zhongda Tech K3 Industrial Edge AI Module: 60 TOPS RISC-V on Mini COM-E

SpacemiT K3 SoC in a Mini COM-E module: 8× X100 cores @ 2.2 GHz, 8× A100 AI cores with 60 TOPS, 30B LLM inference, -40 to 70°C industrial temp, 8× CAN-FD, 100% domestic supply chain. Full spec deep dive.

SpacemiT K360 TOPSMini COM-E30B LLM
2026-08-27
RISC-V Datacenter 15 min

SiFive BigSky SF-2U870: First Rackable 2U RISC-V Datacenter Server

32 P870-D cores at 2.0 GHz, 256 GB DDR5-5600, PCIe Gen5, NVMe, and out-of-the-box Ubuntu 26.04 LTS / RHEL 10. Deep dive into the specs, CUDA/NVLink Fusion support, and what it means for RISC-V in the datacenter.

SiFiveBigSkyP870-DCUDA
2026-08-25
WCH MCU 10 min

CH32X035: WCH's All-in-One USB + Type-C PD RISC-V MCU

QingKe V4C RV32IMAC core integrates USB 2.0 full-speed, USB PD 3.0 and Type-C PHYs, a PIOC state-machine I/O controller, dual OPA, triple CMP, 12-bit ADC and 65 KB Flash — collapse any external PD trigger chip.

CH32X035WCHUSB PDType-C
2026-08-22
Development Tools 12 min

Andes RVBuilder: AI-Assisted RISC-V IDE for VS Code

Andes' new VS Code plugin integrates the RISC-V toolchain, debugger, and MCP-based AI agent support. Cross-platform for Windows and Linux, with sample import and natural-language debug control.

AndesRVBuilderVS Code
2026-08-20
RISC-V IP 17 min

StarFive Dubhe-100: First Deliverable Server-Grade RISC-V HPC CPU IP

A 15-stage deep-OoO, 6-issue, 256-entry-window RISC-V core targeting Arm Cortex-A78 at 15/GHz SPECint2006. RVA23-compliant with vector unit and Type 1/2 hypervisor — scalable to 256 cores per die.

StarFiveDubhe-100Server CPU IP
2026-08-19
RISC-V Connectivity 15 min

Timesintelli PT153S: Fully Domestic RISC-V Gigabit USB Ethernet Controller

USB 3.2 Gen1 (5 Gbps) to Gigabit Ethernet on a self-developed RV32IMAC RISC-V core. Pin-compatible, driverless, 1M units in 3 months.

PT153SUSB 3.2 Gen1Gigabit Ethernet
2026-08-18
HPMicro MCU 14 min

HPMicro HPM53M1: 480MHz RISC-V MCU for Robot Joint Control

480MHz RISC-V with FPU/DSP, integrated 150V half-bridge drivers, 4x CAN-FD, 2MSPS ADC, 9x9mm QFN80. Purpose-built for robot joint servo control and already in mass production.

HPM53M1Motor ControlCAN-FD
2026-08-17
SpacemiT K3 Hardware 12 min

SpacemiT K3 Pico-ITX: Compact 60 TOPS RISC-V AI Computer

2.5-inch Pico-ITX plus SBC built around the K3 RVA23 AI CPU. 10GbE SFP+, NVMe, dual M.2, 65W single-cable power, and industrial -40 °C to +85 °C options.

K3Pico-ITXEdge AI
2026-08-15
SpacemiT K3 16 min

SpacemiT K3: Flagship RISC-V AI CPU Deep Dive

8x X100 @ 2.4GHz, 8x A100 AI cores, 60 TOPS, 130K DMIPS. First mass-production RISC-V chip with RVA23, 1024-bit RVV, native FP8, and full chip-level virtualization.

K3RVA2360 TOPS
2026-08-14
SpacemiT K1 Application 10 min

myCobot 280 RISC-V: World's First RISC-V Full-Stack Open-Source Robot Arm

Elephant Robotics + SpacemiT K1 (8-core X60). On-device LLM inference (0.5-1B params, 10+ tokens/s), ROS2, full-stack open source from ISA to robot control code.

SpacemiT K1RoboticsROS2
2026-08-13
RISC-V Ecosystem 12 min

XiangShan + Ruyi: China's Open RISC-V Processor System and Native OS

Deep dive into the XiangShan Kunming Lake open-source RISC-V core and the Ruyi native OS — China's push toward a self-evolving RISC-V hardware/software ecosystem.

XiangShanRuyiRVA23
2026-08-12
WCH High-Performance MCU 15 min

CH32H417: WCH's Dual-Core 400MHz RISC-V MCU with USB 3.0 5Gbps

WCH's first V5F-class flagship. Heterogeneous big.LITTLE: V5F 400MHz + V3F, built-in USB 3.2 Gen 1 5Gbps PHY (measured 450 MB/s), 100M Ethernet PHY, Type-C/PD, dual high-speed ADCs (5 Msps + 20 Msps).

CH32H417QingKe V5FUSB 3.0
2026-08-11
RISC-V AI Chip 14 min

中科通量金刚GC3: RISC-V + Dataflow Architecture for Video AIGC

12 RISC-V cores, 200 TOPS INT8, 128GB unified memory. A dataflow architecture chip that eliminates data搬运 bottlenecks in video generation and understanding.

中科通量DataflowVideo AIGC
2026-08-10
RISC-V IP 16 min

SiFive Performance P570 Gen 3: Data-Center-Grade RISC-V IP

SiFive's third-generation Performance P570 raises the bar for high-performance RISC-V processor cores with RVA23 ISA profile support and out-of-order execution.

SiFiveP570RVA23
2026-08-09
WCH MCU 8 min

CH32V003: The $0.1 RISC-V MCU Getting Started Guide

From bare metal blink to USB device — everything you need to start with the world's cheapest RISC-V microcontroller.

CH32V003QingKe V2AMCU
2026-07-15
WCH MCU 12 min

CH32V317 Deep Dive: USB 2.0 HS + Ethernet PHY on a Single RISC-V Chip

The most connected RISC-V MCU from WCH. 480Mbps USB, 100M Ethernet, 8 UARTs, dual CAN, dual ADC — all on a QingKe V4F core.

CH32V317USB 2.0 HSEthernet
2026-07-10
SpacemiT K1 15 min

SpacemiT K1 OpenWrt SDK: Complete Development Guide

From SDK download to custom firmware build — the complete guide to developing OpenWrt on the K1 RISC-V platform.

K1OpenWrtSDK
2026-07-05
SpacemiT K3 18 min

K3 RVA23 Architecture: Why It Matters for RISC-V

The world's first RVA23-compliant RISC-V chip in mass production. Deep dive into X100 cores, A100 AI engines, and what RVA23 means for software compatibility.

K3RVA23X100
2026-07-01
WCH Tools 10 min

MounRiver Studio: The IDE for WCH RISC-V Development

Complete walkthrough of MounRiver Studio — project setup, debugging, peripheral configuration, and tips for CH32V series development.

MounRiver StudioIDEWCH
2026-06-25
SpacemiT K1 14 min

K1 AI SDK: Running ML Models on RISC-V Hardware

From Docker setup to model deployment — run ASR, vision, and LLM inference on the K1's 2 TOPS AI engine.

K1AISDK
2026-06-20
Industry 16 min

RISC-V vs ARM in 2026: The Real Ecosystem Gap

An honest assessment of where RISC-V stands against ARM in 2026 — where it's winning, where it's still behind, and what changed this year.

RISC-VARMComparison
2026-06-15
WCH MCU 11 min

Building an Industrial Gateway with CH32V307

Practical guide: 8 serial ports, dual CAN, Gigabit Ethernet, and Modbus TCP/RTU conversion on a $3 RISC-V chip.

CH32V307IndustrialGateway
2026-06-10

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