Automotive-Grade RISC-V: Infineon’s AURIX RC1 and the Qualification Stack Behind It
Infineon has been the reference point for automotive microcontrollers for two decades, and for two decades the instruction set underneath AURIX has been proprietary. On 4 November 2026 that ended: the company announced AURIX™ RC1, which its own release calls “Infineon’s first MCU platform that leverages the benefits of RISC-V”. This article separates what Infineon actually specified from what it did not, sets the announcement beside a Chinese automotive RISC-V family that is already sampling, and explains why the decisive layer in this market is the certified toolchain rather than the core.
What Was Actually Announced
On 4 November 2026 in Munich, Infineon introduced AURIX™ RC1 — described in its own release as “Infineon’s first MCU platform that leverages the benefits of RISC-V”. That sentence is the story. AURIX is not an experiment: it is the line the company credits with its position as the world’s largest automotive microcontroller supplier, and RC1 is the first time that line has been re-based onto an open instruction set. Everything else — safety levels, memory sizes, the software ecosystem — is downstream of that decision.
It is also, deliberately, a concept. Infineon will show the RC1 family at electronica 2026 in Munich (10–13 November, Hall C3, Booth 502) and targets samples in the first half of 2027. No part numbers, clocks, process node or prices were published. What was published is the architecture of the platform and the shape of the tiers.
| Item | As announced (4 Nov 2026) | Status |
|---|---|---|
| ISA | RISC-V, open standard instruction set architecture | Stated; no ISA string, no extension list, no profile named |
| 32-bit cores | Up to 12 processing cores | Stated as a family maximum |
| Edge AI | One “advanced parallel processing unit” for edge inference | Stated; no TOPS, no precision formats disclosed |
| Embedded memory | Up to 40 MB | Stated as a family maximum |
| 64-bit tier | Planned lineup extending the MCU family with 64-bit microprocessor capability (hybrid MCU/MPU) | Planned, no timing |
| Functional safety | Designed to support applications up to ASIL D | “Designed to support” — silicon not yet available |
| Security | ISO/SAE 21434 and EU Cyber Resilience Act mechanisms; hardware physical protection; crypto-agility; ready for post-quantum cryptography | Stated; algorithms not named |
| In-vehicle networking | CAN-XL, 10BASE-T1S, multi-Gigabit Ethernet; BRIGHTLANE™ Ethernet switching plus hardware-accelerated data routing on selected devices | Stated |
| Power | Matching OPTIREG™ companion supply portfolio | Stated |
| Software | DRIVECORE ecosystem: AUTOSAR, open-source software, functional safety, cybersecurity; virtual prototypes; AI-assisted migration tooling | Stated; RISC-V MCAL availability not specified |
| Availability | Concept at electronica, 10–13 Nov 2026; samples targeted H1 2027 | Target, not commitment dated to a quarter |
Why a 12-Core MCU Is a Zonal-Architecture Statement
The headline numbers look like a microcontroller that ate a small SoC: twelve 32-bit cores, an AI block, 40 MB of embedded memory. Read against the SDV migration they are a consolidation target. In a zonal architecture, functions that used to live in dozens of separate ECUs move into a handful of zone controllers and a central car computer; each of those boxes then has to run body, chassis, thermal, access and diagnostics workloads at once, with isolation between them.
The mechanism Infineon chose is telling: RC1 is not a new line beside AURIX and TRAVEO™ T2G — it merges them. The release says RC1 “integrates the strengths of AURIX as well as Infineon’s TRAVEO™ T2G family for body, connectivity and display applications into one joint next MCU generation”, spanning zone, body and chassis control, battery management, powertrain, safety management for driver assistance and cockpit — then “further scalability towards cross-domain computing”. Two previously separate MCU families collapsing into one ISA-compatible basis is the part of the announcement that matters more than any core count: it is a software-reuse decision wearing a hardware announcement’s clothes.
RISC-V is what makes that collapse affordable. A fixed ISA forces a vendor to pick one core design and scale it; a modular one lets infineon’s engineers keep a common foundation while optimising individual lineups — the release’s own framing is that “processing resources can be tailored to the specific needs of each application” and that “software, tools, and expertise developed for one domain can be reused and scaled across others”. Whether that modularity delivers in silicon is an open question, but the commercial logic is sound: the cost of a domain-specific MCU today is mostly the duplicated software stack, not the transistors.
The Real Gate Is Not the Core, It Is the Certificate
Automotive is the one market where an ISA argument is nearly worthless on its own. A car OEM does not buy a core; it buys a tool-qualified, safety-documented, AUTOSAR-conformant platform, and the paperwork is the moat. This is why Infineon’s release spends as much space on DRIVECORE as on the silicon: pre-integrated bundles covering AUTOSAR, open-source software, functional safety and cybersecurity, plus virtual prototypes so teams can start before hardware exists and AI-assisted migration tools to move code from existing AURIX and TRAVEO T2G projects.
The same logic explains Infineon’s standards work, which the release lists almost in passing: the company is a premium member of RISC-V International and a founding member of Quintauris, the automotive-focused joint venture, working with partners across tooling, middleware, virtualisation and system development. In this market the shared-industry-foundation play is not charity; it is how you avoid shipping a chip nobody’s certified compiler can target.
The Chinese Counterpart Already Shipping Samples
The clearest way to see how much of automotive RISC-V is still unbuilt is to compare RC1 with a part that already exists. CCDC (国芯科技, China Core Technology) is sampling its CCRC4XXX family — presented by the company as China’s first multi-core RISC-V post-quantum automotive AI MCU. Its disclosed specification is a useful yardstick for what a 2026 automotive RISC-V MCU looks like in production form:
| Item | CCDC CCRC4XXX family |
|---|---|
| Process | 22 nm with embedded RRAM |
| CPU | Multi-core RISC-V; two sampling SKUs — CCRC4088S (8+4 cores, 500 MHz, 14,000 DMIPS, high-precision analog front end, GTM4.1) and CCRC4046S (4+4 cores, 500 MHz, 7,000 DMIPS) |
| NPU | 0.3 TOPS AI subsystem |
| Functional safety | ASIL D |
| Security | EVITA Full-class HSM, post-quantum and classical algorithms, NIST FIPS 203 / FIPS 204 (ML-KEM / ML-DSA) support |
| Data movement | CGDMA hardware routing for low-latency, high-throughput in-vehicle traffic |
| Target domains | 4088S: central domain control and ADAS; 4046S: body, BMS and zonal controllers |
CCDC’s ecosystem list is the more instructive half of the story, because it enumerates exactly the layer Infineon is still assembling. CCDC published the following as qualified or adapted against CCRC4XXX:
| Layer | Vendor / product | Qualification claim |
|---|---|---|
| Compiler / IDE | HighTec automotive C/C++ and Rust compiler toolchain | ASIL D certified toolchain, covering the full CCDC architecture range |
| Compiler / IDE | IAR Embedded Workbench for RISC-V | Functional-safety edition certified by TÜV SÜD; C-STAT static analysis; MISRA C/C++ support |
| Compiler / IDE | TASKING toolchain with winIDEA debug | Full compile-assemble-link-debug flow |
| Debug probes | SEGGER J-Link | Up to 4 MB/s download; plug-and-play support |
| Debug / trace | Lauterbach TRACE32 | Multi-core and heterogeneous SoC debug, AUTOSAR-aware debugging, code coverage |
| Classic AUTOSAR | NeuSAR CP (Neusoft Reach) | AUTOSAR R21-11 / R23-11, multi-core deployment, ISO 26262 ASIL D certified basic software; >130 automotive chips adapted |
| Open-source AUTOSAR | “Xiaoman” V25.10 (Isoft / “open-source Xiaoman”) | Adapted to the CCRC4 series; the wider Xiaoman programme claims 158 adapted chips and RISC-V support |
Set the two announcements side by side and the market structure becomes visible. Infineon is entering with a platform concept, a house software ecosystem and 2027 samples; CCDC is entering with silicon in customers’ hands and a third-party-qualified toolchain list. Neither has published the one datum that would let an engineer reason about portability: the ISA string. CCDC says “multi-core RISC-V”, Infineon says “RISC-V”, and both stop there.
The Missing Datum: An ISA String
For application-class RISC-V, the industry has been converging on published profiles — the RVA family — precisely so that binary portability can be argued about. Automotive MCU-class parts sit outside that convergence: each vendor picks its own extension set, its own memory map and its own safety island architecture, and the practical consequence is that “AUTOSAR ported to RISC-V” today still means “AUTOSAR ported to this RISC-V”.
| Question a tier-1 must answer | Disclosed on 4 Nov 2026? |
|---|---|
Which ratified extensions are implemented (Zc*, P, DSP/SIMD,
bit-manipulation, vector, matrix, custom opcodes)? | No — neither vendor |
| Are custom extensions required to reach the DMIPS figures, and can they be disabled? | No |
| Lockstep or redundant core arrangement for ASIL D? | No |
Which compiler version and -march string is inside the certified build? |
No |
| Is the safety manual available under NDA only? | No |
Five Things to Watch Before H1 2027
- ISA disclosure at electronica. If RC1’s booth material names extensions and profiles rather than saying “RISC-V”, the platform is further along than the release suggests.
- Which DRIVECORE components ship for RISC-V on day one. The hard part is not the AUTOSAR runtime — it is the MCAL drivers and the safety documentation behind them. A late MCAL turns a 2027 sample into a 2028 project.
- Whether the 64-bit tier is the same ISA. A hybrid MCU/MPU family only pays off if the 32-bit and 64-bit parts share a toolchain and a memory model; if they do not, the consolidation argument weakens considerably.
- Named lead customers. Tier-1 design wins — not “in discussion with” — are the only proof that the qualification stack is finished.
- Whether the two ecosystems converge. If DRIVECORE, NeuSAR, Xiaoman and the certified compilers all end up supporting the same core configurations, automotive RISC-V becomes one target. If each vendor’s toolchain only knows its own cores, the market reproduces the fragmentation RISC-V was supposed to remove.
The Takeaway
For a decade the honest summary of RISC-V in automotive was “interesting cores, no qualification”. As of this week both halves have credible answers in flight: a top-tier incumbent has committed its flagship MCU line to the open ISA with a 2027 sampling target, and a Chinese vendor is already putting post-quantum, ASIL D parts into customer hands with a TÜV-certified compiler stack behind them. The remaining unknown is not whether RISC-V can do automotive control — it plainly can — but whether the toolchain, the MCAL and the safety case will arrive together, on schedule, for the same core configuration across vendors.
一句话结论：2026 年 11 月 4 日，英飞凌在慕尼黑发布 AURIX™ RC1 —— 这是其旗舰车规 MCU 产品线首次改用开放指令集 RISC-V 作为基础架构；同一周，国产的国芯科技 CCRC4XXX 系列已在向客户送样。 两件事合起来说明：车规 RISC-V 的竞争焦点已经不在核，而在工具链认证与基础软件。
英飞凌 RC1 官方披露了什么：最多 12 个 32 位核、1 个面向边缘 AI 的 并行处理单元、最高 40 MB 片上存储；规划中还有一条增加 64 位 微处理器能力的混合 MCU/MPU 产品线；面向最高 ASIL D；网络安全机制对标 ISO/SAE 21434 与欧盟《网络弹性法案》，具备密码敏捷性并预留后量子密码能力；车载网络支持 CAN-XL、10BASE-T1S、多千兆以太网，部分型号集成 BRIGHTLANE 交换与硬件加速路由；配套 OPTIREG 电源；软件侧是 DRIVECORE 生态（AUTOSAR、开源软件、功能安全、信息安全、 虚拟原型、AI 辅助迁移）。2026 年 11 月 10–13 日慕尼黑 electronica 展出概念， 计划 2027 年上半年出样。
没披露的同样重要：没有 ISA 字符串、没有扩展列表、没有主频、工艺节点、缓存层级、 锁步架构，也没有任何 benchmark。因此本文不给这些数字 —— 所有表格数据均出自英飞凌官方新闻稿 infpr202611-026。
结构性看点在产品线合并：RC1 不是 AURIX 旁边再加一条线，而是把 AURIX 与 TRAVEO™ T2G（车身/连接/显示）合并成下一代统一 MCU 基础，覆盖区域控制、 车身底盘、BMS、动力、智驾安全管理与座舱，并向跨域计算延伸。两个原本独立的 MCU 家族收敛到同一套 ISA 兼容基础，本质是软件复用决策，而不是单纯的硬件发布。
国产对照：国芯科技 CCRC4XXX。官方口径为国内首款基于 RISC-V 多核架构的抗量子车规 AI MCU：22nm RRAM 工艺、0.3 TOPS NPU、ASIL D、EVITA Full 级 HSM，兼容抗量子与传统密码算法， 支持 NIST FIPS 203/204（ML-KEM / ML-DSA）。两款送样型号：CCRC4088S（8+4 核， 500 MHz，14,000 DMIPS，高精度模拟前端 + GTM4.1，面向中央域控/智驾）与 CCRC4046S（4+4 核，500 MHz，7,000 DMIPS，面向车身/BMS/区域域控）。 需注意：同一篇官方稿内的宣传图与公司 2026 半年报还出现 CCRC4086S（6+6 核，500 MHz， 10,500 DMIPS）与 CCRC4045S（4+2 核，400 MHz，5,600 DMIPS）， 型号命名在不同来源间不一致，选型前必须与厂商确认。
真正的护城河是证书不是核：国芯公布的适配名单恰好把这条链路摊开了 —— HighTec（ASIL D 认证 C/C++ 与 Rust 工具链）、IAR Embedded Workbench for RISC-V（TÜV SÜD 认证功能安全版、C-STAT、MISRA C/C++）、TASKING、 SEGGER J-Link（4 MB/s）、Lauterbach TRACE32（多核/异构调试、 AUTOSAR 感知调试、代码覆盖率）；基础软件侧有东软睿驰 NeuSAR CP（AUTOSAR R21-11/R23-11、 多核部署、ISO 26262 ASIL D 认证、已适配 130+ 车规芯片）与普华 开源小满 V25.10。
两家都缺同一个数据：ISA 字符串。英飞凌只说 RISC-V，国芯只说多核 RISC-V。没有扩展集、
没有认证编译器里的 -march、没有锁步架构，Tier-1 就无法判断某个认证编译器版本是否覆盖该核配置、
手写汇编能否跨硅片版本存活、今天的代码能否迁移到下一颗 SKU。在服役周期以十五年计的市场里，这是采购
决策而不是文档细节。
接下来看五件事：① electronica 上是否公布 ISA 扩展与 profile；② DRIVECORE 的 RISC-V MCAL 是否随样片同时到位（AUTOSAR 运行时是容易的部分）；③ 64 位产品线是否与 32 位同 ISA、 同工具链；④ 是否有具名 Tier-1 定点；⑤ 各家生态是否收敛到同一核配置 — 否则 RISC-V 会在车规侧 复制它本来要消除的碎片化。
Суть: 4 ноября 2026 года Infineon представила AURIX™ RC1 — первую платформу MCU компании на открытой архитектуре RISC-V, и это не боковая линейка, а перевод флагманской автомобильной серии на открытый набор инструкций. В те же дни китайская CCDC уже отгружает образцы семейства CCRC4XXX. Вывод: борьба в automotive RISC-V идёт не за ядро, а за сертификацию инструментов и базовое ПО.
Что заявлено по RC1: до 12 32-битных ядер, блок параллельной обработки для edge AI, до 40 MB встроенной памяти; планируется линейка с 64-битными возможностями (гибрид MCU/MPU); расчёт на уровень ASIL D; механизмы по ISO/SAE 21434 и EU Cyber Resilience Act, крипто-гибкость и готовность к постквантовой криптографии; CAN-XL, 10BASE-T1S, мультигигабитный Ethernet, на части устройств — коммутатор BRIGHTLANE и аппаратная маршрутизация; сопутствующие PMIC OPTIREG; экосистема DRIVECORE (AUTOSAR, open source, функциональная безопасность, кибербезопасность, виртуальные прототипы, ИИ-инструменты миграции). Показ концепта — electronica в Мюнхене 10–13 ноября 2026, образцы — первое полугодие 2027.
Чего не раскрыли: строку ISA, список расширений, частоту, техпроцесс, иерархию кэша, схему lockstep и какие-либо бенчмарки. Поэтому в таблицах ниже этих чисел нет: всё взято из официального пресс-релиза infpr202611-026.
Главное структурно: RC1 объединяет AURIX и TRAVEO™ T2G (кузов, подключение, дисплеи) в одно следующее поколение MCU с общей базой — от зональных контроллеров до BMS, силовой электроники, систем безопасности ADAS и кокпита. Это решение о переиспользовании ПО, а не только о кремнии.
Китайский аналог: CCDC CCRC4XXX — 22 нм с встроенной RRAM, NPU 0.3 TOPS, ASIL D, HSM класса EVITA Full, поддержка NIST FIPS 203/204 (ML-KEM / ML-DSA). Образцы: CCRC4088S (8+4 ядра, 500 МГц, 14 000 DMIPS, GTM4.1) и CCRC4046S (4+4 ядра, 500 МГц, 7 000 DMIPS). В графике того же релиза и в отчёте за первое полугодие фигурируют также CCRC4086S (6+6, 500 МГц, 10 500 DMIPS) и CCRC4045S (4+2, 400 МГц, 5 600 DMIPS) — нумерация в источниках расходится, перед выбором нужно уточнять у поставщика.
Сертификация важнее ядра: список CCDC показывает весь слой, который Infineon ещё собирает: HighTec (ASIL D, C/C++ и Rust), IAR Embedded Workbench for RISC-V (версия с сертификатом TÜV SÜD, C-STAT, MISRA), TASKING, SEGGER J-Link, Lauterbach TRACE32; AUTOSAR — NeuSAR CP (R21-11/R23-11, ASIL D, более 130 чипов) и открытый Xiaoman V25.10.
Общий пробел: ни один не опубликовал строку ISA. Без расширений, -march
сертифицированного компилятора и данных о lockstep интегратор не может судить о переносимости сборки.
Для рынка с 15-летним жизненным циклом это вопрос закупки, а не документации.
Conclusión en una línea: el 4 de noviembre de 2026 Infineon anunció AURIX™ RC1, su primera plataforma de MCU basada en el conjunto de instrucciones abierto RISC-V — no una línea lateral, sino la reubicación de su familia automotriz insignia. Al mismo tiempo, la china CCDC ya envía muestras de la familia CCRC4XXX. La batalla del RISC-V automotriz no está en el núcleo, sino en la cualificación de herramientas y el software base.
Lo declarado para RC1: hasta 12 núcleos de 32 bits, una unidad de proceso paralelo para IA en el borde y hasta 40 MB de memoria embebida; se prevé una línea con capacidades de 64 bits (híbrido MCU/MPU); diseñado para aplicaciones hasta ASIL D; mecanismos según ISO/SAE 21434 y el Reglamento europeo de Ciberresiliencia, cripto-agilidad y preparación para criptografía poscuántica; CAN-XL, 10BASE-T1S y Ethernet multi-gigabit, con conmutación BRIGHTLANE y enrutado acelerado por hardware en algunos dispositivos; alimentación OPTIREG; ecosistema DRIVECORE (AUTOSAR, código abierto, seguridad funcional, ciberseguridad, prototipos virtuales, migración asistida por IA). Concepto en electronica (Múnich, 10–13 de noviembre de 2026); muestras previstas para el primer semestre de 2027.
Lo que no se publicó: la cadena ISA, la lista de extensiones, la frecuencia, el nodo de proceso, la jerarquía de caché, el esquema lockstep ni ningún benchmark. Por eso no aparecen aquí: todas las cifras provienen del comunicado oficial infpr202611-026.
El punto estructural: RC1 fusiona AURIX y TRAVEO™ T2G (carrocería, conectividad, pantallas) en una única generación de MCU con base común, desde control zonal hasta BMS, tren motriz, gestión de seguridad para ADAS y cockpit. Es una decisión de reutilización de software, no solo de silicio.
Contraparte china: CCRC4XXX — 22 nm con RRAM embebida, NPU de 0,3 TOPS, ASIL D, HSM clase EVITA Full y soporte de NIST FIPS 203/204 (ML-KEM / ML-DSA). Muestras: CCRC4088S (8+4 núcleos, 500 MHz, 14 000 DMIPS, GTM4.1) y CCRC4046S (4+4 núcleos, 500 MHz, 7 000 DMIPS). El material gráfico del mismo comunicado y el informe semestral citan además CCRC4086S (6+6, 500 MHz, 10 500 DMIPS) y CCRC4045S (4+2, 400 MHz, 5 600 DMIPS): la nomenclatura difiere entre fuentes y debe confirmarse con el proveedor.
La certificación manda: la lista de CCDC muestra la capa que Infineon aún está montando: HighTec (ASIL D, C/C++ y Rust), IAR Embedded Workbench for RISC-V (edición certificada por TÜV SÜD, C-STAT, MISRA), TASKING, SEGGER J-Link, Lauterbach TRACE32; en AUTOSAR, NeuSAR CP (R21-11/R23-11, ASIL D, más de 130 chips) y el abierto Xiaoman V25.10.
El dato ausente en ambos: la cadena ISA. Sin extensiones, sin el -march del
compilador certificado y sin información de lockstep, un Tier-1 no puede juzgar la portabilidad de la
compilación. En un mercado con ciclos de vida de quince años, eso es una decisión de compra.
En une phrase : le 4 novembre 2026, Infineon a annoncé AURIX™ RC1, sa première plateforme de microcontrôleurs fondée sur le jeu d’instructions ouvert RISC-V — non pas une gamme parallèle, mais le rebasage de sa famille automobile phare. Au même moment, le chinois CCDC échantillonne déjà la famille CCRC4XXX. L’enjeu du RISC-V automobile n’est donc pas le cœur, mais la qualification des outils et du logiciel de base.
Ce qui est annoncé pour RC1 : jusqu’à 12 cœurs 32 bits, une unité de traitement parallèle pour l’IA embarquée, jusqu’à 40 Mo de mémoire intégrée ; une gamme prévue avec des capacités 64 bits (hybride MCU/MPU) ; conçu pour des applications jusqu’à ASIL D ; mécanismes conformes à ISO/SAE 21434 et au règlement européen sur la cyber-résilience, crypto-agilité et préparation à la cryptographie post-quantique ; CAN-XL, 10BASE-T1S et Ethernet multi-gigabit, avec commutation BRIGHTLANE et routage accéléré sur certains composants ; alimentation OPTIREG ; écosystème DRIVECORE (AUTOSAR, open source, sécurité fonctionnelle, cybersécurité, prototypes virtuels, migration assistée par IA). Concept à electronica (Munich, 10–13 novembre 2026), échantillons visés au premier semestre 2027.
Ce qui n’est pas publié : la chaîne ISA, la liste des extensions, la fréquence, le nœud de gravure, la hiérarchie de cache, l’architecture lockstep et tout benchmark. Ces chiffres sont donc absents ici : toutes les données proviennent du communiqué officiel infpr202611-026.
Le point structurel : RC1 fusionne AURIX et TRAVEO™ T2G (carrosserie, connectivité, affichage) en une seule génération de MCU à base commune, du contrôle zonal au BMS, au groupe motopropulseur, à la gestion de sécurité ADAS et au cockpit. C’est une décision de réutilisation logicielle autant qu’un choix de silicium.
Contrepartie chinoise : CCRC4XXX — 22 nm avec RRAM intégrée, NPU 0,3 TOPS, ASIL D, HSM de classe EVITA Full, prise en charge de NIST FIPS 203/204 (ML-KEM / ML-DSA). Échantillons : CCRC4088S (8+4 cœurs, 500 MHz, 14 000 DMIPS, GTM4.1) et CCRC4046S (4+4 cœurs, 500 MHz, 7 000 DMIPS). Les visuels du même communiqué et le rapport semestriel citent aussi CCRC4086S (6+6, 500 MHz, 10 500 DMIPS) et CCRC4045S (4+2, 400 MHz, 5 600 DMIPS) : la nomenclature varie selon les sources et doit être confirmée auprès du fournisseur.
La certification prime : la liste CCDC révèle la couche qu’Infineon assemble encore : HighTec (ASIL D, C/C++ et Rust), IAR Embedded Workbench for RISC-V (édition certifiée TÜV SÜD, C-STAT, MISRA), TASKING, SEGGER J-Link, Lauterbach TRACE32 ; côté AUTOSAR, NeuSAR CP (R21-11/R23-11, ASIL D, plus de 130 puces) et l’ouvert Xiaoman V25.10.
Le point manquant chez les deux : la chaîne ISA. Sans extensions, sans le -march
du compilateur certifié et sans détail lockstep, un équipementier ne peut pas évaluer la portabilité du build.
Sur un marché à cycle de vie de quinze ans, c’est une décision d’achat.
Fazit in einem Satz: Am 4. November 2026 stellte Infineon in München AURIX™ RC1 vor — die erste MCU-Plattform des Unternehmens auf Basis der offenen Befehlssatzarchitektur RISC-V. Das ist keine Nebenlinie, sondern die Neuausrichtung der Automotive-Kerngattung; parallel liefert CCDC aus China bereits Muster der Familie CCRC4XXX. Der Wettbewerb entscheidet sich damit nicht am Kern, sondern an Tool-Qualifizierung und Basissoftware.
Was für RC1 genannt wurde: bis zu 12 32-Bit-Kerne, eine parallele Verarbeitungseinheit für Edge-KI, bis zu 40 MB integrierter Speicher; geplant ist eine Linie mit zusätzlichen 64-Bit-Fähigkeiten (MCU/MPU-Hybrid); ausgelegt für Anwendungen bis ASIL D; Sicherheitsmechanismen nach ISO/SAE 21434 und EU Cyber Resilience Act, Krypto-Agilität und Bereitschaft für Post-Quanten-Kryptografie; CAN-XL, 10BASE-T1S, Multi-Gigabit-Ethernet, bei ausgewählten Bausteinen mit BRIGHTLANE-Switching und hardwarebeschleunigtem Routing; OPTIREG-Stromversorgung; Ökosystem DRIVECORE (AUTOSAR, Open Source, Funktionssicherheit, Cybersicherheit, virtuelle Prototypen, KI-gestützte Migration). Konzept auf der electronica in München (10.–13. November 2026), Muster für das erste Halbjahr 2027 angekündigt.
Was fehlt: ISA-String, Liste der Erweiterungen, Takt, Fertigungsnode, Cache-Hierarchie, Lockstep-Architektur und jegliche Benchmarks. Deshalb stehen diese Zahlen hier nicht — alle Werte stammen aus der offiziellen Pressemitteilung infpr202611-026.
Der strukturelle Punkt: RC1 führt AURIX und TRAVEO™ T2G (Karosserie, Konnektivität, Displays) zu einer gemeinsamen MCU-Generation zusammen — von Zonensteuergeräten über BMS und Antriebsstrang bis zu Sicherheitsmanagement für ADAS und Cockpit. Das ist eine Software-Wiederverwendungsentscheidung, nicht nur Silizium.
Pendant aus China: CCRC4XXX — 22 nm mit integriertem RRAM, 0,3 TOPS NPU, ASIL D, HSM der Klasse EVITA Full, Unterstützung für NIST FIPS 203/204 (ML-KEM / ML-DSA). Muster: CCRC4088S (8+4 Kerne, 500 MHz, 14 000 DMIPS, GTM4.1) und CCRC4046S (4+4 Kerne, 500 MHz, 7 000 DMIPS). Grafik im selben Release und der Halbjahresbericht nennen zusätzlich CCRC4086S (6+6, 500 MHz, 10 500 DMIPS) und CCRC4045S (4+2, 400 MHz, 5 600 DMIPS) — die Nomenklatur weicht zwischen den Quellen ab und muss beim Hersteller bestätigt werden.
Zertifizierung entscheidet: Die CCDC-Liste zeigt genau die Schicht, die Infineon noch baut: HighTec (ASIL D, C/C++ und Rust), IAR Embedded Workbench for RISC-V (TÜV SÜD-zertifizierte Safety-Edition, C-STAT, MISRA), TASKING, SEGGER J-Link, Lauterbach TRACE32; bei AUTOSAR NeuSAR CP (R21-11/R23-11, ASIL D, über 130 Chips) und das offene Xiaoman V25.10.
Die bei beiden fehlende Angabe: der ISA-String. Ohne Erweiterungen, ohne den
-march-Wert des zertifizierten Compilers und ohne Lockstep-Details kann ein Tier-1 die
Portabilität eines Builds nicht beurteilen. Bei 15-Jahres-Lebenszyklen ist das eine
Beschaffungsentscheidung.
خلاصه در یک خط: در ۴ نوامبر ۲۰۲۶، Infineon در مونیخ AURIX™ RC1 را معرفی کرد — نخستین سکوی میکروکنترلر این شرکت بر پایهٔ معماری مجموعهدستورالعمل باز RISC-V. این یک خط فرعی نیست؛ بازپایهگذاری خانوادهٔ اصلی خودرویی است. همزمان شرکت چینی CCDC نمونههای خانوادهٔ CCRC4XXX را ارسال میکند. نتیجه: رقابت در RISC-V خودرویی نه بر سر هسته، بلکه بر سر صلاحیتدهی ابزارها و نرمافزار پایه است.
آنچه برای RC1 اعلام شد: تا ۱۲ هستهٔ ۳۲ بیتی، یک واحد پردازش موازی برای هوش مصنوعی لبه و تا ۴۰ مگابایت حافظهٔ درونتراشهای؛ خط تولیدی برنامهریزیشده با توانمندی ۶۴ بیتی (ترکیبی MCU/MPU)؛ طراحی برای کاربردهای تا سطح ASIL D؛ سازوکارهای امنیتی مطابق ISO/SAE 21434 و قانون تابآوری سایبری اروپا، چابکی رمزنگاری و آمادگی برای رمزنگاری پساکوانتومی؛ CAN-XL، 10BASE-T1S و اترنت چندگیگابیتی، در برخی قطعات با سوئیچ BRIGHTLANE و مسیریابی شتابیافته با سختافزار؛ تغذیهٔ OPTIREG؛ و زیستبوم DRIVECORE (AUTOSAR، نرمافزار متنباز، ایمنی عملکردی، امنیت، نمونهٔ مجازی، مهاجرت بهکمک هوش مصنوعی). نمایش مفهوم در نمایشگاه electronica مونیخ (۱۰ تا ۱۳ نوامبر ۲۰۲۶) و هدف نمونهسازی نیمهٔ نخست ۲۰۲۷.
آنچه اعلام نشد: رشتهٔ ISA، فهرست افزونهها، فرکانس، گرهٔ ساخت، سلسلهمراتب کش، ساختار lockstep و هیچ محک عملکردی. از اینرو این اعداد در این نوشته نیامدهاند؛ همهٔ دادهها از بیانیهٔ رسمی infpr202611-026 است.
نکتهٔ ساختاری: RC1 خانوادههای AURIX و TRAVEO™ T2G (بدنه، اتصال، نمایشگر) را در یک نسل مشترک MCU ادغام میکند — از کنترل ناحیهای تا BMS، پیشرانه، مدیریت ایمنی ADAS و کابین. این تصمیمی دربارهٔ بازاستفادهٔ نرمافزار است، نه فقط سیلیکون.
همتای چینی: CCRC4XXX — ۲۲ نانومتر با RRAM درونتراشهای، NPU با ۰٫۳ TOPS، ASIL D، HSM کلاس EVITA Full و پشتیبانی از NIST FIPS 203/204 (ML-KEM / ML-DSA). نمونهها: CCRC4088S (۸+۴ هسته، ۵۰۰ مگاهرتز، ۱۴٬۰۰۰ DMIPS، GTM4.1) و CCRC4046S (۴+۴ هسته، ۵۰۰ مگاهرتز، ۷٬۰۰۰ DMIPS). تصویر همان بیانیه و گزارش نیمهٔ سال نیز CCRC4086S (۶+۶، ۵۰۰ مگاهرتز، ۱۰٬۵۰۰ DMIPS) و CCRC4045S (۴+۲، ۴۰۰ مگاهرتز، ۵٬۶۰۰ DMIPS) را ذکر میکنند؛ نامگذاری میان منابع متفاوت است و باید با سازنده تأیید شود.
گواهینامه تعیینکننده است: فهرست CCDC دقیقاً همان لایهای را نشان میدهد که Infineon هنوز میسازد: HighTec (ASIL D، C/C++ و Rust)، IAR Embedded Workbench for RISC-V (نسخهٔ ایمنی با گواهی TÜV SÜD، C-STAT، MISRA)، TASKING، SEGGER J-Link، Lauterbach TRACE32؛ در AUTOSAR نیز NeuSAR CP (R21-11/R23-11، ASIL D، بیش از ۱۳۰ تراشه) و Xiaoman V25.10 متنباز.
دادهٔ غایب در هر دو: رشتهٔ ISA. بدون افزونهها، بدون مقدار -march کامپایلر
گواهیشده و بدون جزئیات lockstep، یک Tier-1 نمیتواند دربارهٔ قابلیت انتقال بیلد داوری کند. در بازاری با
چرخهٔ عمر پانزدهساله، این یک تصمیم خرید است نه یک جزئیات مستندات.
Sources / 参考来源
- Infineon Technologies — “Infineon redefines real-time compute and control for software-defined vehicles and Physical AI with new AURIX™ RC1”, Munich, 4 November 2026 (infpr202611-026) — primary source for all RC1 figures
- Infineon press-release index — confirms 4 Nov 2026 publication date alongside the Qualcomm Snapdragon Ride item of 2 Nov 2026
- SEMI China — full Chinese-language text of the AURIX RC1 release (12 cores, 40 MB, ASIL D, CAN-XL / 10BASE-T1S / BRIGHTLANE, DRIVECORE, electronica 10–13 Nov)
- IT之家 via Tencent News (4 Nov 2026) — Chinese summary confirming sample timeline H1 2027
- CCDC (国芯科技) official account — CCRC4XXX family, CCRC4088S / CCRC4046S sampling parts, 22 nm RRAM, 0.3 TOPS NPU, FIPS 203/204, toolchain and AUTOSAR adaptation list
- Reprint of the CCDC article (Shenzhen Automotive Electronics Industry Association) — same specification text, third-party copy
- CCDC H1 2026 results coverage — CCRC4 series process/positioning plus the CCRC4045S / CCRC4086S naming variant and the HighTec / TASKING / SEGGER / Lauterbach adaptation list
- RISC-V International news index — no AURIX RC1 statement as of 5 November 2026; Infineon’s premium membership and Quintauris founding role are stated in the Infineon release itself