Overview

Epic Semi introduced Contrail AIX (Contrail Compute 5000 Series CPU+AI Superchip) at RISC-V Summit Europe 2026 (Bologna, June 8–12). Epic positions the platform as the “world’s first RISC-V AI Execution Platform” — not a training accelerator, but infrastructure purpose-built for the inference + reasoning + agentic + RAG workloads that define the post-training era.

The design consolidates CPU orchestration and AI execution into a single chip. The value proposition is structural: instead of streaming data and weights to a discrete GPU over PCIe, the AI acceleration cores sit on the same die and share memory coherently with the RISC-V cores, eliminating the “memory copy” latency and power penalty that traditional CPU+GPU systems pay on every inference call.

Headline Claim

32 server-class RISC-V scalar cores + 16 integrated AI acceleration cores = 48-core heterogeneous design, up to 75 TOPS (INT8). Fully RVA23-compliant, supports RVV 1.0 and the new Vector Matrix Extension (VME). 4-channel DDR5-6400 up to 1 TB, 64-lane PCIe Gen5, CXL 2.0 memory expansion.

Compute Subsystem

Scalar Cores

32 high-performance server-class RISC-V cores — RVA23-compatible, single-core performance rated at >16/GHz SPECint2006. The cores support the RISC-V Hypervisor Extension (H Extension), giving native Type-1 and Type-2 hypervisor capability for cloud-native virtualization stacks (KVM, Kubernetes, Docker).

AI Acceleration Cores

16 integrated AI cores share a hardware-accelerated matrix computation engine. Combined throughput reaches 75 TOPS (INT8) with native support for INT4, INT8, FP16, FP32, and additional AI data formats. The accelerators are tightly coupled to the scalar cores via a coherent fabric, so inference calls don’t need explicit data movement.

RVV 1.0 + Vector Matrix Extension (VME)

The scalar cores execute RVV 1.0 vector code, while the AI engines implement the new Vector Matrix Extension (VME). VME introduces dedicated matrix-multiply-accumulate instructions that operate directly on the vector register file — the same model that drove AVX-512 + AMX adoption on x86. For RISC-V it removes the need to keep hand-rolling matrix kernels as long vector loops and is expected to become the standard AI extension across RVA23 server chips going forward.

Memory & I/O

DDR5 Memory

4-channel DDR5 at up to 6400 MT/s, scaling to 1 TB of system memory per socket. That’s the kind of capacity tier that lets you host a dense retrieval-augmented generation index entirely in DRAM, with the agent loop staying close to the data.

PCIe Gen5 + CXL 2.0

64 lanes of PCIe Gen5 with bifurcation support, plus a separate PCIe Gen3 expansion path. CXL 2.0 memory expansion lets a chassis pool CXL-attached memory across nodes — useful for KV-cache sharing, vector-database staging, and memory-bound retrieval workloads that don’t fit into local DDR5.

I/O Virtualization

RISC-V IOMMU with MSI interrupt virtualization — so virtual machines can directly assign NICs, NVMe controllers, and accelerators without host-mediated I/O. RISC-V AIA 1.0 (Advanced Interrupt Architecture) is supported for high-performance MSI/MSI-X routing in guest VMs.

Enterprise Virtualization & Security

Contrail AIX is designed to drop into the same operational stack as an x86 or Arm server:

Software Stack

The platform is not delivered as bare hardware — Epic includes (or certifies) the full cloud-native open-source stack out of the box:

The IREE choice matters: MLIR-based compilation lets you take a model authored once (PyTorch, JAX, ONNX) and lower it through the same toolchain to the RVV 1.0 vector units on the scalar cores and the VME matrix engines, so a single model graph can be partitioned and scheduled across both fabrics.

Workload Targets

Epic’s message is consistent with what RISC-V International has been saying since the Server Platform Spec 1.0 ratification: 2026 is the year RVA23-class server silicon arrives, and the workloads to focus on are post-training AI — not greenfield training clusters. Concretely:

Reference Server Configuration

The launch ships a 1U-class enterprise server around the superchip:

ComponentSpecification
CPU+AI Superchip1× Contrail Compute 5000 Series (RVA23 + VME)
Memory256 GB DDR5 (4× 64 GB @ 6400 MHz), upgradable to 1 TB
Boot / OS Drive1× 1 TB NVMe M.2 SSD
Data Drives2× 7.68 TB NVMe SSDs
Network1× OCP 3.0 NIC (Broadcom 57414, 10/25 GbE)
Power Supply1300 W Platinum efficiency
Cooling4× 80 mm fan modules, high-performance heatsink with air duct
PCIe64 lanes PCIe Gen5 + PCIe Gen3 expansion

A future dual-socket variant, Contrail Compute 5050, scales single-core performance further and supports up to 4 TB DDR5, positioning it for HPC and large-model training-adjacent research workloads while keeping the open-RISC-V foundation.

Why This Matters for the RISC-V Ecosystem

Contrail AIX sits at the center of the broader 2026 RISC-V inflection point:

The Volta / Hopper-class “train bigger, run bigger” mantra doesn’t apply when the question is “how do I orchestrate 50 agents across a private cloud without burning 50 H100s?” Contrail AIX targets exactly that workload with a fully open ISA, open firmware, and open cloud stack.

Official Resources